Patent US3893033A successfully refreshed from Google Patents.
US3893033A
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Apparatus for producing timing signals that are synchronized with asynchronous data signals
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-05-02
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Granted: 1975-07-01
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Expires: 1994-05-02
Abstract
Abstract Apparatus which includes a pair of inverters, a NOR-gate and three up/down counters is connected to a source of asynchronous data signals and a source of oscillator signals. The apparatus uses the data signals and the oscillator signals to develop timing signals that are synchronized with the asynchronous data signals.
Inventors
- 👤 Dever C Finch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:46
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
191 words
Apparatus for producing timing signals that are synchronized with asynchronous data signals, for use with a source of data and a source of oscillator signals, said apparatus comprising: first and second up/down counters each having first and second input leads and an output lead, said first input lead of said first counter being connected to said source of data, said source of oscillator signals being connected to said second input leads of said first and said second counters; an inverter, said inverter being connected between said source of data and said first input lead of said second counter; a logic gate having first and second input leads and an output lead, said first input lead of said gate being connected to said output lead of said first counter, said second input lead of said gate being connected to said output lead of said second counter; and a shift register having first and second input leads and a plurality of output leads, said first input lead of said register being connected to said source of data, said second input lead of said register being connected to said output lead of said gate.
Claim 2
Dependent Claim
191 words
Apparatus for producing timing signals that are synchronized with asynchronous data signals, for use with a source of data and a source of oscillator signals, said apparatus comprising: first and second up/down counters each having first and second input leads and an output lead, said first input lead of said first counter being connected to said source of data, said source of oscillator signals being connected to said second input leads of said first and said second counters; an inverter, said inverter being connected between said source of data and said first input lead of said second counter; a logic gate having first and second input leads and an output lead, said first input lead of said gate being connected to said output lead of said first counter, said second input lead of said gate being connected to said output lead of said second counter; and a shift register having first and second input leads and a plurality of output leads, said first input lead of said register being connected to said source of data, said second input lead of said register being connected to said output lead of said gate.
Claim 3
Dependent Claim
45 words
Apparatus for producing timing signals as defined in claim 1 including: a third up/down counter having first and second input leads and first and second output leads, said first input lead of said third counter being connected to said output lead of said logic gate.
Claim 4
Dependent Claim
256 words
Apparatus for producing timing signals that are synchronized with asynchronous data signals, for use with a source of data and a source of oscillator signals, said apparatus comprising: first, second and third up/down counters each having first and second input leads and first and second output leads, said first input lead of said first counter being connected to said source of data, said source of oscillator signals being connected to said second input leads of said first, said second and said third counters; first and second inverters, said first inverter being connected between said source of data and said first input lead of said second counter; an OR-gate having first and second input leads and an output lead, said first input lead of said OR-gate being connected to said first output lead of said first counter, said second input lead of said OR-gate being connected to said first output lead of said second counter, said second inverter being connected between said output lead of said OR-gate and said first input lead of saiD third counter; a shift register having first and second input leads and a plurality of output leads, said first input lead of said register being connected to said source of data, said second input lead of said register being connected to said output lead of said OR-gate; and first and second output terminals, said first output terminal being connected to said first output lead of said third counter, said second output terminal being connected to said second output lead of said third counter.
Claim 5
Dependent Claim
256 words
Apparatus for producing timing signals that are synchronized with asynchronous data signals, for use with a source of data and a source of oscillator signals, said apparatus comprising: first, second and third up/down counters each having first and second input leads and first and second output leads, said first input lead of said first counter being connected to said source of data, said source of oscillator signals being connected to said second input leads of said first, said second and said third counters; first and second inverters, said first inverter being connected between said source of data and said first input lead of said second counter; an OR-gate having first and second input leads and an output lead, said first input lead of said OR-gate being connected to said first output lead of said first counter, said second input lead of said OR-gate being connected to said first output lead of said second counter, said second inverter being connected between said output lead of said OR-gate and said first input lead of saiD third counter; a shift register having first and second input leads and a plurality of output leads, said first input lead of said register being connected to said source of data, said second input lead of said register being connected to said output lead of said OR-gate; and first and second output terminals, said first output terminal being connected to said first output lead of said third counter, said second output terminal being connected to said second output lead of said third counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |