Patent US3892956A successfully refreshed from Google Patents.
US3892956A
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Cascade digital fast fourier analyzer
Assignee: AT&T Inc
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Filing: 1971-12-27
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Granted: 1975-07-01
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Expires: 1991-12-27
Abstract
Abstract A single-input-channel cascade FFT processor is described which includes a plurality of cascaded arithmetic units interconnected by delay and switching elements. All components are operated at full capacity without the requirement that the input sequence be reordered in a digits-reversed or other manner.
Inventors
- 👤 Peter Siegfried Fuss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:20
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/14; G06F17/141; G06F17/142
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
317 words
A fast Fourier transform processor for forming Fourier coefficient signals corresponding to consecutive N-sample records of a single sequence of ordered input samples, each sample appearing during a respective consecutive fixed 1/2R-second interval of time, R being a constant value, comprising a plurality of ordered cascaded processing stages A. the first of which stages comprises 1. an arithmetic unit having first and second input terminals and first and second output terminals for generating at said output terminals during successive fixed 1/R-second intervals of time pairs of output signals representing the sum and difference of a first product signal and a signal applied at said first input terminal, said first product signal representing the product of a signal applied at said second input terminal and a predetermined weighting factor, and 2. means for applying, during 2M consecutive ones of said fixed 1/R-second intervals of time, M > N/2 successive pairs of said input samples of consecutive N-sample records of said single sequence to said first and second input terminals during said successive fixed intervals of time while excluding other signals from said input terminals, said pairs each including a selected sample from the first half of one of said N-sample records of input samples and a uniquely corresponding sample from the second half of said one of said N-sample records of input samples, B. each stage after the first comprising 1. a pair of input terminals, 2. a pair of output terminals, 3. a network for selectively delaying signals applied at said input terminals, 4. arithmetic means for forming output pairs of signals corresponding to the sum and difference of a second product signal and a signal applied at said pair of input terminals and selectively delayed by said network, said second product signal representing the product of a predetermined weighting factor and another signal applied at said pair of input terminals and selectively delayed by said network.
Claim 2
Dependent Claim
317 words
A fast Fourier transform processor for forming Fourier coefficient signals corresponding to consecutive N-sample records of a single sequence of ordered input samples, each sample appearing during a respective consecutive fixed 1/2R-second interval of time, R being a constant value, comprising a plurality of ordered cascaded processing stages A. the first of which stages comprises 1. an arithmetic unit having first and second input terminals and first and second output terminals for generating at said output terminals during successive fixed 1/R-second intervals of time pairs of output signals representing the sum and difference of a first product signal and a signal applied at said first input terminal, said first product signal representing the product of a signal applied at said second input terminal and a predetermined weighting factor, and 2. means for applying, during 2M consecutive ones of said fixed 1/R-second intervals of time, M > N/2 successive pairs of said input samples of consecutive N-sample records of said single sequence to said first and second input terminals during said successive fixed intervals of time while excluding other signals from said input terminals, said pairs each including a selected sample from the first half of one of said N-sample records of input samples and a uniquely corresponding sample from the second half of said one of said N-sample records of input samples, B. each stage after the first comprising 1. a pair of input terminals, 2. a pair of output terminals, 3. a network for selectively delaying signals applied at said input terminals, 4. arithmetic means for forming output pairs of signals corresponding to the sum and difference of a second product signal and a signal applied at said pair of input terminals and selectively delayed by said network, said second product signal representing the product of a predetermined weighting factor and another signal applied at said pair of input terminals and selectively delayed by said network.
Claim 3
Dependent Claim
99 words
means for applying, during 2M consecutive ones of said fixed 1/R-second intervals of time, M > N/2 successive pairs of said input samples of consecutive N-sample records of said single sequence to said first and second input terminals during said successive fixed intervals of time while excluding other signals from said input terminals, said pairs each including a selected sample from the first half of one of said N-sample records of input samples and a uniquely corresponding sample from the second half of said one of said N-sample records of input samples, B. each stage after the first comprising
Claim 4
Dependent Claim
99 words
means for applying, during 2M consecutive ones of said fixed 1/R-second intervals of time, M > N/2 successive pairs of said input samples of consecutive N-sample records of said single sequence to said first and second input terminals during said successive fixed intervals of time while excluding other signals from said input terminals, said pairs each including a selected sample from the first half of one of said N-sample records of input samples and a uniquely corresponding sample from the second half of said one of said N-sample records of input samples, B. each stage after the first comprising
Claim 5
Dependent Claim
5 words
a pair of output terminals,
Claim 6
Dependent Claim
5 words
a pair of output terminals,
Claim 7
Dependent Claim
32 words
The processor of claim 1 wherein said network comprises first and second serial delay means and a switch for selectively connecting said delay means between said input terminals and said arithmetic means.
Claim 8
Dependent Claim
50 words
The processor of claim 2 wherein at the ith of said stages, i 2, 3, . . . , m, m log2N, saiD first and second delay means each comprises means for delaying selected output signals from the (i - 1)th stage by an amount equal to 2m-i sample pairs.
Claim 9
Dependent Claim
11 words
a network for selectively delaying signals applied at said input terminals,
Claim 10
Dependent Claim
11 words
a network for selectively delaying signals applied at said input terminals,
Claim 11
Dependent Claim
63 words
arithmetic means for forming output pairs of signals corresponding to the sum and difference of a second product signal and a signal applied at said pair of input terminals and selectively delayed by said network, said second product signal representing the product of a predetermined weighting factor and another signal applied at said pair of input terminals and selectively delayed by said network.
Claim 12
Dependent Claim
63 words
arithmetic means for forming output pairs of signals corresponding to the sum and difference of a second product signal and a signal applied at said pair of input terminals and selectively delayed by said network, said second product signal representing the product of a predetermined weighting factor and another signal applied at said pair of input terminals and selectively delayed by said network.
References Cited (Backward Citations)
US3588460A
Cited
US3816729A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |