High-precision digital-to-analog converters

Claim 1

A digital-to-analog converter comprising: a first plurality of terminals including n digital input terminals of different binary rank, an analog output terminal and a ground terminal, n being an integer greater than 1; a first resistive ladder network with n first sections connected between said output and ground terminals, said sections including first series resistors of magnitude R and first branch resistors of magnitude 2R forming n first junctions; a second resistive ladder network with j second sections connected between said output and ground terminals in parallel with said first ladder network, j being an integer smaller than n, said second sections including second series resistors of magnitude R and second branch resistors of magnitude 2R forming j second junctions; a resistive connection of magnitude greater than R between said output terminal and said second ladder network; n first impedance-adapting means with substantially zero outpuT impedance connecting each of said input terminals with a respective first junction, the separation of said first junctions from said output terminal decreasing with increasing ranks of the input terminals connected thereto; j second impedance-adapting means with substantially zero output impedance connecting the j highest-ranking input terminals with a respective second junction; and rupturable connector means between said j highest-ranking input terminals and said second impedance-adapting means enabling calibration of said first ladder network by selective disconnection of any of said second impedance-adapting means from the corresponding input terminals with resulting modification of the output voltage of said first ladder network due to energization of said corresponding input terminals.