US3750141A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for the controlled energization of a load
Assignee: Italtel SpA
•
Filing: 1971-10-28
•
Granted: 1973-07-31
•
Expires: 1991-10-28
Abstract
Abstract A binary-analog converter comprises a decoding matrix in the form of a ladder-type R/2R network having its several junctions connected to respective input circuits for energization by a signal representing a bit of a code word to be translated. Each input circuit includes a main transistor, continuously energized from a stabilized voltage source, and a pair of switching transistors in two parallel branches cascaded therewith, one branch leading to the associated junction point while the other one includes a dummy load of magnitude 2R/3. The two switching transistors are alternately turned on, depending upon the value of the corresponding bit.
Inventors
- 👤 I Poretti
- 👤 G Bernasconi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 05:56
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
199 words
A system for converting a combination of binary input signals into an analog output, comprising: a resistive ladder network with series and terminal resistances of magnitude R and with shunt resistances of magnitude 2R, said network forming a plurality of junctions between its series and shunt resistances; an individual energizing circuit connected to each of said junctions, said energizing circuit including a main transistor, a first ancillary transistor between said main transistor and the corresponding junction, and a second ancillary transistor between said main transistor and a resistive dummy load of magnitude 2R/3 individual to each energizing circuit; a constant-voltage source common to all energizing circuits for maintaining said main transistors thereof conductive with an internal resistance which is high compared to R; and switch means for alternately driving one ancillary transistor of each energizing circuit to conduction while simultaneously cutting off the other ancillary transistor thereof in response to changes in the binary value of a respective input signal, said network being provided with an output lead at a point common to one of said terminal resistances and an outgoing series resistance for generation of an analog signal synthesized from all input signals as weighted by said network.
Claim 2
Independent Claim
199 words
A system for converting a combination of binary input signals into an analog output, comprising: a resistive ladder network with series and terminal resistances of magnitude R and with shunt resistances of magnitude 2R, said network forming a plurality of junctions between its series and shunt resistances; an individual energizing circuit connected to each of said junctions, said energizing circuit including a main transistor, a first ancillary transistor between said main transistor and the corresponding junction, and a second ancillary transistor between said main transistor and a resistive dummy load of magnitude 2R/3 individual to each energizing circuit; a constant-voltage source common to all energizing circuits for maintaining said main transistors thereof conductive with an internal resistance which is high compared to R; and switch means for alternately driving one ancillary transistor of each energizing circuit to conduction while simultaneously cutting off the other ancillary transistor thereof in response to changes in the binary value of a respective input signal, said network being provided with an output lead at a point common to one of said terminal resistances and an outgoing series resistance for generation of an analog signal synthesized from all input signals as weighted by said network.
Claim 3
Dependent Claim
47 words
A system as defined in claim 1 wherein said main and ancillary transistors are of like conductivity type and are each provided with a base, an emitter and a collector, the collector of said main transistor being connected in parallel to the emitters of said switching transistors.
Claim 4
Dependent Claim
42 words
A system as defined in claim 2 wherein said switch means comprises a first base lead for said first ancillary transistor carrying said input signal and a second base lead for said second ancillary transistor carrying the complement of said input signal.
Claim 5
Dependent Claim
22 words
A system as defined in claim 1 wherein the transistors of all said energizing circuits are closely juxtaposed in a common environment.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-07-30 | 1977-01-29 | 1977-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-07-30 | 1981-01-29 | 1981-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-07-30 | 1985-01-29 | 1985-07-31 | $7700.00 | Window Closed / Lapsed |