Bar geometry verification system for bar-coded characters

Claim 1

A system for the verification of the geometry of bar coded characters including a. a clocked bar interval counter; b. a bar edge signal carrying line connected to said counter to restart the bar interval count of said counter at each bar edge signal carried by said line; c. a clocked too narrow flip-flop set by each bar edge signal carried by said line and reset by a relatively low count of said counter; d. a clocked too wide flip-flop set by each bar edge signal carried by said line and reset by a relatively high count of said counter; e. an OR-gate combining the output of said too narrow flip-flop and said too wide flip-flop; f. an error flip-flop set by a character presence signal and reset by the output of said OR-gate; g. clocked first logic circuitry controlled by said counter for generating a signal when a bar edge signal occurs during a period from a time when the count of said counter equals a first number exceeding said relatively low count to a time when the count of said counter equals a second number smaller than said relatively high count, said first logic circuitry being connected to said error flip-flop to clear said error flip-flop by said signal; h. a second logic circuitry for sensing voltage errors caused by insufficient bar height connected to said error flip-flop to clear said error flip-flop in response to said voltage errors; i. a second OR-gate for combining the output of said first logic circuitry and the output of said second logic circuitry; j. said OR-gate and said second OR-gate being implemented by a first and second NAND-gate; and k. an inverter interposed between said second NAND-gate and said error flip-flop.

Claim 2

A system for the verification of the geometry of bar coded characters including a. a clocked bar interval counter; b. a bar edge signal carrying line connected to said counter to restart the bar interval count of said counter at each bar edge signal carried by said line; c. a clocked too narrow flip-flop set by each bar edge signal carried by said line and reset by a relatively low count of said counter; d. a clocked too wide flip-flop set by each bar edge signal carried by said line and reset by a relatively high count of said counter; e. an OR-gate combining the output of said too narrow flip-flop and said too wide flip-flop; f. an error flip-flop set by a character presence signal and reset by the output of said OR-gate; g. clocked first logic circuitry controlled by said counter for generating a signal when a bar edge signal occurs during a period from a time when the count of said counter equals a first number exceeding said relatively low count to a time when the count of said counter equals a second number smaller than said relatively high count, said first logic circuitry being connected to said error flip-flop to clear said error flip-flop by said signal; h. a second logic circuitry for sensing voltage errors caused by insufficient bar height connected to said error flip-flop to clear said error flip-flop in response to said voltage errors; i. a second OR-gate for combining the output of said first logic circuitry and the output of said second logic circuitry; j. said OR-gate and said second OR-gate being implemented by a first and second NAND-gate; and k. an inverter interposed between said second NAND-gate and said error flip-flop.

Claim 3

A system for the verification of the geometry of bar coded characters including a. a clocked bar interval counter connected to a bar edge signal carrying line to restart said counter at each bar edge signal carried by said line; b. a first clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce too narrow signals if the count of said counter is less than a predetermined number; c. a second clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce a too wide signal if the count of said counter exceeds a predetermined number; d. an OR-gate for combining said too narrow signal and said too wide signal; e. a clocked error flip-flop having at least two inputs in addition to the clock input thereof, one of said additional inputs being supplied with a character presence signal and the other of said additional inputs being supplied with the output of said OR-gate; f. both said first flip-flop and said second flip-flop being J-K flip-flops, the J-input of said first flip-flop and of said second flip-flop being bar edge signals; g. said OR-gate being implemented by a NAND-gate; h. the K-input of said first flip-flop being connected to said counter to receive a signal when a relatively small count of said counter occurs and the Q output of said first flip-flop being connected to one of the input terminals of said NAND-gate; and i. the K-input of said second flip-flop being connected to said counter to receive a signal when a relatively large count of said counter occurs, and the Q output of said second flip-flop being connected by the intermediary of an inverter to the other of the input terminals of said NAND-gate.

Claim 4

A system for the verification of the geometry of bar coded characters including a. a clocked bar interval counter connected to a bar edge signal carrying line to restart said counter at each bar edge signal carried by said line; b. a first clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce too narrow signals if the count of said counter is less than a predetermined number; c. a second clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce a too wide signal if the count of said counter exceeds a predetermined number; d. an OR-gate for combining said too narrow signal and said too wide signal; e. a clocked error flip-flop having at least two inputs in addition to the clock input thereof, one of said additional inputs being supplied with a character presence signal and the other of said additional inputs being supplied with the output of said OR-gate; f. both said first flip-flop and said second flip-flop being J-K flip-flops, the J-input of said first flip-flop and of said second flip-flop being bar edge signals; g. said OR-gate being implemented by a NAND-gate; h. the K-input of said first flip-flop being connected to said counter to receive a signal when a relatively small count of said counter occurs and the Q output of said first flip-flop being connected to one of the input terminals of said NAND-gate; and i. the K-input of said second flip-flop being connected to said counter to receive a signal when a relatively large count of said counter occurs, and the Q output of said second flip-flop being connected by the intermediary of an inverter to the other of the input terminals of said NAND-gate.

Claim 5

A system for the verification of the geometry of bar coded characters including a. a clocked bar interval counter connected to a bar edge signal carrying line to restart said counter at each bar edge signal carried by said line; b. a first clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce too narrow signals if the count of said counter is less than a predetermined number. c. a second clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce a too wide signal if the count of said counter exceeds a predetermined number; d. an OR-gate for combining said too narrow signal and said too wide signal; e. a clocked error flip-flop having at least two inputs in addition to the clock input thereof, one of said additional inputs being supplied with a character presence signal and the other of said additional inputs being supplied with the output of said OR-gate; and f. said error flip-flop being a J-K flip-flop having a clear input terminal, the J-input of said error flip-flop being supplied with a character presence signal, the K-input of said error flip-flop being supplied with the output of said OR-gate and said clear input terminal of said error flip-flop being supplied with a signal indicative of other error conditions than indicated by the output of said OR-gate.

Claim 6

A system for the verification of the geometry of bar coded characters including a. a clocked bar interval counter connected to a bar edge signal carrying line to restart said counter at each bar edge signal carried by said line; b. a first clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce too narrow signals if the count of said counter is less than a predetermined number. c. a second clocked flip-flop set at each bar edge signal carried by said line and connected to said counter to produce a too wide signal if the count of said counter exceeds a predetermined number; d. an OR-gate for combining said too narrow signal and said too wide signal; e. a clocked error flip-flop having at least two inputs in addition to the clock input thereof, one of said additional inputs being supplied with a character presence signal and the other of said additional inputs being supplied with the output of said OR-gate; and f. said error flip-flop being a J-K flip-flop having a clear input terminal, the J-input of said error flip-flop being supplied with a character presence signal, the K-input of said error flip-flop being supplied with the output of said OR-gate and said clear input terminal of said error flip-flop being supplied with a signal indicative of other error conditions than indicated by the output of said OR-gate.