US3889134A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tunnel diode digital data sample, decision and hold circuit
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1974-05-16
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Granted: 1975-06-10
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Expires: 1994-05-16
Abstract
Abstract A high speed circuit for sampling and reconstructing a nonreturn to zero data input. The circuit essentially consists of a Goto pair, that is of a matched pair of tunnel diodes biased in such a way that one of them will switch to the injection region upon the arrival of both the digital data and a clock signal. The Goto pair is connected to a back diode which will become conductive when one of the Goto pair switches. The Goto pair will provide a return to zero signal which is changed again by a memory circuit to a nonreturn to zero signal. The memory circuit follows the back diode and includes an additional tunnel diode loaded for bistable operation.
Inventors
- 👤 Jack K Basham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:05
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; H; H03; H03K; H03K3/00; H03K3/02; H03K3/313; H03K3/315
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
218 words
A high speed sample, decision and hold circuit for sampling and reconstructing a nonreturn to zero digital data input, said circuit comprising: a. a first and a second tunnel diode, the cathode of said first diode being directly connected to the anode of said second dIode to form junction point; b. means for applying the nonreturn to zero data to said junction point; c. means coupled to said first and said second diode for biasing and balancing said diodes to form a Goto pair; d. means for applying a clock signal of opposite polarity to said first and second diodes so that each diode is supplied with a clock signal of a predetermined polarity, whereby the data in conjunction with the clock signal will drive a selected one of said diodes into its injection region; e. a memory circuit including a third tunnel diode; f. means for biasing said third diode so that it is in a bistable condition; and g. coupling means for coupling said first junction point to said third tunnel diode and for applying the voltage at said first junction point to said third diode to drive it from one stable state to the other or for maintaining it in its previous stable state depending upon the decision made by said first and second diodes.
Claim 2
Dependent Claim
218 words
A high speed sample, decision and hold circuit for sampling and reconstructing a nonreturn to zero digital data input, said circuit comprising: a. a first and a second tunnel diode, the cathode of said first diode being directly connected to the anode of said second dIode to form junction point; b. means for applying the nonreturn to zero data to said junction point; c. means coupled to said first and said second diode for biasing and balancing said diodes to form a Goto pair; d. means for applying a clock signal of opposite polarity to said first and second diodes so that each diode is supplied with a clock signal of a predetermined polarity, whereby the data in conjunction with the clock signal will drive a selected one of said diodes into its injection region; e. a memory circuit including a third tunnel diode; f. means for biasing said third diode so that it is in a bistable condition; and g. coupling means for coupling said first junction point to said third tunnel diode and for applying the voltage at said first junction point to said third diode to drive it from one stable state to the other or for maintaining it in its previous stable state depending upon the decision made by said first and second diodes.
Claim 3
Dependent Claim
16 words
A circuit as defined in claim 1 wherein said coupling means consists of a back diode.
Claim 4
Dependent Claim
30 words
A circuit as defined in claim 1 wherein said coupling means consists of an amplifier followed by at least two further diodes connected in parallel to form a conductive loop.
Claim 5
Dependent Claim
15 words
A circuit as defined in claim 3 wherein said further diodes are hot carrier diodes.
Claim 6
Dependent Claim
206 words
A high speed sample, decision and hold circuit for sampling and reconstructing a nonreturn to zero digital data input, said circuit comprising: a. a first and a second tunnel diode, the cathode of said first diode being directly connected to the anode of said second diode to form a junction point; b. means for supplying the nonreturn to zero data to said first junction point; c. means for applying a clock signal of opposite polarity respectively to the anode of said first diode and the cathode of said second diode; d. means connected to the anode of said first diode and the cathode of said second diode for biasing and balancing said diodes to form a Goto pair and so that the data in conjunction with the clock signal will force a selected one of said diodes into the injection region; e. a memory circuit including a third tunnel diode; f. means connected to said third diode for biasing it to be in a bistable state; and g. coupling means for coupling said junction point to said third diode and including a unilaterally conducting device for driving said third diode into one of its stable states in response to the voltage at said first junction point.
Claim 7
Dependent Claim
206 words
A high speed sample, decision and hold circuit for sampling and reconstructing a nonreturn to zero digital data input, said circuit comprising: a. a first and a second tunnel diode, the cathode of said first diode being directly connected to the anode of said second diode to form a junction point; b. means for supplying the nonreturn to zero data to said first junction point; c. means for applying a clock signal of opposite polarity respectively to the anode of said first diode and the cathode of said second diode; d. means connected to the anode of said first diode and the cathode of said second diode for biasing and balancing said diodes to form a Goto pair and so that the data in conjunction with the clock signal will force a selected one of said diodes into the injection region; e. a memory circuit including a third tunnel diode; f. means connected to said third diode for biasing it to be in a bistable state; and g. coupling means for coupling said junction point to said third diode and including a unilaterally conducting device for driving said third diode into one of its stable states in response to the voltage at said first junction point.
Claim 8
Dependent Claim
24 words
A circuit as defined in claim 5 wherein said coupling means consists of a back diode having its cathode connected to said junction point.
Claim 9
Dependent Claim
35 words
A circuit as defined in claim 5 wherein said coupling means consists of an amplifier and at least two further diodes connected in parallel to form a conductive loop connected to said third tunnel diode.
Claim 10
Dependent Claim
15 words
A circuit as defined in claim 7 wherein said further diodes are hot carrier diodes.
Claim 11
Dependent Claim
34 words
A circuit as defined in claim 5 wherein said clock signals of opposite polarity are applied to the anode of said first diode and the cathode of said second diode by a respective resistor.
Claim 12
Dependent Claim
44 words
A circuit as defined in claim 5 wherein said first and second diodes are so biased that one of them will be triggered by the combination of the data and the clock signal whereupon the triggered diode will subsequently return to its low point.
References Cited (Backward Citations)
US3510679A
Cited
US3603818A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-09 | 1978-12-09 | 1979-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-09 | 1982-12-09 | 1983-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-09 | 1986-12-09 | 1987-06-10 | $7700.00 | Window Closed / Lapsed |