Abstract A field effect transistor with small gate leakage current; the gate leakage current being substantially reduced by a lowtemperature glass layer formed on a portion of the surface. It is well known that an inversion layer occurs in a P-type region under an oxide layer, such as silicon dioxide, by ions contained in the oxide layer and/or electric fields applied between the Ptype region and a conductive layer formed thereon. In a field effect transistor, the inversion layer increases the leakage current by decreasing the impurity concentration at the surface of the semiconductor body. This is especially true in the P-type region. This decrease of impurity concentration lowers the input impedance. The present invention replaces an oxide layer on a Ptype region with a low-temperature glass layer and substantially reduces or eliminates gate leakage current.
A FIELD EFFECT TRANSISTOR COMPRISING A SUBSTRATE OF SILICON OF ONE CONDUCTIVITY TYPE, A SECOND REGION OF OPPOSITE CONDUCTIVITY TYPE DIFFUSED INTO SAID FIRST REGION FORMING A FIRST PN JUNCTION THEREBETWEEN, A THIRD HIGH IMPURITY REGION OF THE FIRST CONDUCTIVITY TYPE DIFFUSED INTO SAID SECOND REGION FORMING A SECOND PN JUNCTION THEREBETWEEN AND HAVING A THIN CHANNEL BETWEEN SAID FIRST AND THIRD REGIONS, OPPOSITE END REGIONS OF SAID CHANNEL RISING TO THE SURFACE OF SAID SUBSTRATE AND PROVIDING SOURCE AND DRAIN REGIONS OF HIGH SECONDTYPE IMPURITY CONCENTRATION, A GATE ELECTRODE ON SAID THIRD REGION, A THERMALLY GROWN SILICON DIOXIDE LAYER FORMED ON THE UPPER SURFACE OF SAID SUBSTRATE AND SAID SECOND REGION OVERLYING THE SURFACE TERMINATION OF SAID FIRST AND SECOND PN JUNCTIONS AND LEAVING AT LEAST A PORTION OF SAID SURFACE OF SAID SUBSTRATE AND SAID THIRD REGION FREE, A LOW-TEMPERATURE SILICON DIOXIDE GLASS LAYER FORMED ON THE REMAINING UPPER SURFACE PORTION OF SAID SUBSTRATE NOT COVERED BY SAID THERMALLY GROWN SILICON DIOXIDE
Claim 2
Dependent Claim
164 words
A FIELD EFFECT TRANSISTOR COMPRISING A SUBSTRATE OF SILICON OF ONE CONDUCTIVITY TYPE, A SECOND REGION OF OPPOSITE CONDUCTIVITY TYPE DIFFUSED INTO SAID FIRST REGION FORMING A FIRST PN JUNCTION THEREBETWEEN, A THIRD HIGH IMPURITY REGION OF THE FIRST CONDUCTIVITY TYPE DIFFUSED INTO SAID SECOND REGION FORMING A SECOND PN JUNCTION THEREBETWEEN AND HAVING A THIN CHANNEL BETWEEN SAID FIRST AND THIRD REGIONS, OPPOSITE END REGIONS OF SAID CHANNEL RISING TO THE SURFACE OF SAID SUBSTRATE AND PROVIDING SOURCE AND DRAIN REGIONS OF HIGH SECONDTYPE IMPURITY CONCENTRATION, A GATE ELECTRODE ON SAID THIRD REGION, A THERMALLY GROWN SILICON DIOXIDE LAYER FORMED ON THE UPPER SURFACE OF SAID SUBSTRATE AND SAID SECOND REGION OVERLYING THE SURFACE TERMINATION OF SAID FIRST AND SECOND PN JUNCTIONS AND LEAVING AT LEAST A PORTION OF SAID SURFACE OF SAID SUBSTRATE AND SAID THIRD REGION FREE, A LOW-TEMPERATURE SILICON DIOXIDE GLASS LAYER FORMED ON THE REMAINING UPPER SURFACE PORTION OF SAID SUBSTRATE NOT COVERED BY SAID THERMALLY GROWN SILICON DIOXIDE
Claim 3
Dependent Claim
40 words
A field effect transistor according to claim 1, in which drain and source electrodes aRe formed on the surface of said silicon nitride layer and extend through windows respectively through all of said layers to said source and drain regions.