Debounce logic for keyboard

Claim 2

Debounce logiC for use with a keyboard having a plurality of selectively actuable sequentially scanned keyswitches; each of said keyswitches being operable between a first steady state condition and a second steady state condition and initiating a first signal (A) in response thereto comprising: first digital storage means receiving said first signal (A) from a selected keyswitch; first logic means responsive to said first signal (A) and a second signal (B) provided at the output of said first digital storage means and related to the operative condition of said selected keyswitch during a previous scan; said first logic means supplying a third signal (D, E) to a second digital storage means in response to a predetermined condition of said first (A) and second (B) signals; and means for synchronizing the stepping of said signals through said first and second digital storage means whereby said second digital storage means provides an output signal (F, G) in response to a steady state condition of said selected keyswitch as indicated by the same operative condition during consecutive scans.

Claim 3

The apparatus of claim 1 wherein said first logic means provides said third signal (D) in response to the simultaneous presence of said first (A) and second (B) signals.

Claim 4

The apparatus of claim 2 which further includes second logic means responsive to said third signal (D) and the output (F) of said second digital storage means and provides a transitory signal (G) in response to the change of the key from the first steady state condition to the second steady state condition.

Claim 5

The apparatus of claim 2 which further includes third logic means responsive to at least one of said first (A) and second (B) signals and providing an output signal (E) to said second digital storage means whereby said output signal (F) from said second digital storage means changes level upon the operation of said key from the second steady state condition to the first steady state condition.

Claim 6

The apparatus of claim 1 wherein said first logic means is responsive to at least one of said first (A) or second (B) signals and provides said third signal (E) to said second digital storage means whereby said output signal (F) from said second digital storage means changes level in response to the operation of the key from the second steady state condition to the first steady state condition.

Claim 7

The apparatus of claim 5 which further includes second logic means providing a fourth signal (D) to said second digital storage means in response to the simultaneous presence of said first (A) and second (B) signals.

Claim 8

The apparatus of claim 6 which further includes third logic means responsive to said fourth signal (D) and the output (F) of said second digital storage means and providing a transitory signal (G) upon the operation of the key from the first steady state condition to the second steady state condition.

Claim 9

The apparatus of claim 2 which further includes third digital storage means receiving the output (B) of said first digital storage means and providing a third signal (C) to said first logic means; said first logic means including a first AND-gate receiving said first (A) second (B) and third (C) signals and feeding an output signal (D) to a second gating means and said second digital storage means whereby said signal (D) is fed to the input of said second digital storage means upon the simultaneous presence of said first (A) second (B) and third (C) signals in response to the operation of the key from the first steady state condition to the second steady state condition.

Claim 10

The apparatus of claim 8 which further includes a second AND-gate; one input of said second AND-gate being connected to the output of said first AND-gate and an alternate input of said second AND-gate responsive to the output (F) of said second digital storage means.

Claim 11

The apparatus of claim 9 which further iNcludes an OR-gate, the inputs of said OR-gate receiving said first (A) second (B) and third (C) signals and the output of said OR-gate being fed to one input of a third AND-gate an alternate input of said third AND-gate receiving the output (F) of said second digital storage means and the output of said third AND-gate feeding the input of said second digital storage means.

Claim 12

The apparatus of claim 5 which further includes a third digital storage means receiving the output (B) of said first digital storage means and providing a third (C) signal and the output of which is fed to one input of an AND-gate an alternate input of said AND-gate receiving the output (F) of said second digital storage means and the output (E) of said first AND-gate feeding the input of said second digital storage means.

Claim 13

The apparatus of claim 11 which further includes a second AND-gate receiving said first (A), second (B) and third (C) signals and feeding an output signal (D) to said second digital storage means and to the input of a third AND-gate the alternate input of said third AND-gate being responsive to the output (F) of said second digital storage means.

Claim 16

In combination with a system for producing control signals in response to the state of operation of a make or break switch contact, of the type wherein the state of the switch is periodically sampled during successive time cycles, the system being of the type wherein it sometimes gives ''''extraneous'''' signals, defined as signals which appear to indicate the state of the contact but which are present for a time interval less than X consecutive sampling cycles, X being a preset small whole number greater than 1; a debounce logic circuit for screening out such extraneous signals, which comprises: means for providing X sequential, distinct status signals, a first one of said status signals indicates the sampled state of the contact during the present sampling cycle, and the additional ones of said status signals indicate the state of the contact during the X-1 previous cycles, said status signal providing means including time-delay means for providing the X-1 additional status signals related to the state of the switch during the X-1 previous sampling cycles; and logic means, responsive only to all X status signals, for providing an output control signal which assumes a first level only after all X input signals have indicated a made state of the contact during X consecutive cycles, and control signal thereafter changes to a second level only after all X status signals have indIcated a broken state of the contact during X consecutive cycles.

Claim 17

In combination with a system for producing control signals in response to the state of operation of a make or break switch contact, of the type wherein the state of the switch is periodically sampled during successive time cycles, the system being of the type wherein it sometimes gives ''''extraneous'''' signals, defined as signals which appear to indicate the state of the contact but which are present for a time interval less than X consecutive sampling cycles, X being a preset small whole number greater than 1; a debounce logic circuit for screening out such extraneous signals, which comprises: means for providing X sequential, distinct status signals, a first one of said status signals indicates the sampled state of the contact during the present sampling cycle, and the additional ones of said status signals indicate the state of the contact during the X-1 previous cycles, said status signal providing means including time-delay means for providing the X-1 additional status signals related to the state of the switch during the X-1 previous sampling cycles; and logic means, responsive only to all X status signals, for providing an output control signal which assumes a first level only after all X input signals have indicated a made state of the contact during X consecutive cycles, and control signal thereafter changes to a second level only after all X status signals have indIcated a broken state of the contact during X consecutive cycles.

Claim 18

A debounce logic circuit as recited in claim 14, for use in a system wherein it is desired to produce a single output operating pulse to operate a controlled mechanism only whenever the contact has been in a first state for X consecutive sampling cycles and thereafter changes to a second state and remains in the second state for X consecutive cycles, further comprising: an additional time delay means for delaying the output control signal for a predetermined time delay; second logic means, responsive to all X input signals simultaneously indicating that the contact has been in the second state for X consecutive cycles, for initially generating the output operating pulse; and means, responsive to the output control signal after said additional time delay, for preventing a second operation of said second logic means until after the contact has changed to the first state and has remained in the first state for X consecutive cycles.