US3886541A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Exponential ramp a/d converter
Assignee: Boeing North American Inc
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Filing: 1973-04-25
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Granted: 1975-05-27
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Expires: 1993-04-25
Abstract
Abstract An analog to digital converter which converts an analog signal to a digital signal. The analog signal is representative of a particular analog function or phenomenon and is digitized for use in a digital computer or the like. A ramp signal source establishes a control signal which is used in the A/D converter. High and low voltage limits are established for the circuit operation. These high and low level limits control the active and inactive portions of the circuit. Logic circuitry operates in response to the level limits to selectively activate or inactivate portions of the digitizing circuit and to establish a control function for the ramp circuit.
Inventors
- 👤 George A Watson
- 👤 John J Bollinger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:56
CPC Classifications
F; F02; F02D; F02D41/00; F02D41/009; F02D41/24; F02D41/2403; F02D41/30; F02D41/32; F02D41/34; F02M; F02M51/00; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/58; Y; Y02; Y02T; Y02T10/00; Y02T10/10; Y02T10/40
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
231 words
In combination, ramp signal generating means, voltage divider means, comparator means connected to said ramp signal generating means and said voltage divider network in order to produce a signal representative of the relationship between signals produced by said ramp signal generating means and said voltage divider network, logic means connected to said comparator means to produce an output signal as a function of the signal produced by said comparator means, recirculating register means for producing an output signal representative of the digital signal, said recirculating register means connected to said logic circuit means to have the operation thereof controlled by the signals produced by said logic circuit means, said recirculating register means including output register means connected to supply output signals to a utilization device, first register means connected to selectively supply a portion of the contents thereof to said output register, first adder means for receiving said portion of the contents of said first register means, second register means connected to selectively receive the contents of said first adder means where the contents of said first adder means is the sum of the contents of said second register means and said portion of the contents of said first register means, and second adder means for adding the contents of said first register means to the contents of said second register means and selectively storing same in said first register means.
Claim 2
Dependent Claim
231 words
In combination, ramp signal generating means, voltage divider means, comparator means connected to said ramp signal generating means and said voltage divider network in order to produce a signal representative of the relationship between signals produced by said ramp signal generating means and said voltage divider network, logic means connected to said comparator means to produce an output signal as a function of the signal produced by said comparator means, recirculating register means for producing an output signal representative of the digital signal, said recirculating register means connected to said logic circuit means to have the operation thereof controlled by the signals produced by said logic circuit means, said recirculating register means including output register means connected to supply output signals to a utilization device, first register means connected to selectively supply a portion of the contents thereof to said output register, first adder means for receiving said portion of the contents of said first register means, second register means connected to selectively receive the contents of said first adder means where the contents of said first adder means is the sum of the contents of said second register means and said portion of the contents of said first register means, and second adder means for adding the contents of said first register means to the contents of said second register means and selectively storing same in said first register means.
Claim 3
Dependent Claim
68 words
The combination recited in claim 1 wherein said voltage divider means includes a plurality of impedance elements at least one of which is variable, said voltage divider means producing a plurality of different voltages, said ramp signal generating means includes an RC circuit, and separate comparator means connected to compare the ramp signal produced by said ramp signal generating means and each of said plurality of different voltages.
Claim 4
Dependent Claim
42 words
The combination recited in claim 1 wherein said first register means includes a most significant bit portion and a least significant bit portion, said portion of the contents of said first register represents said most significant bit portion and an overflow condition.
Claim 5
Dependent Claim
50 words
The combination recited in claim 3 including logic means connected between said comparator means and each of said first and second register means to control the operation thereof whereby said first and second register means operate at different times as a function of the signal produced by said comparator means.
Claim 6
Dependent Claim
59 words
The combination recited in claim 1 including control means connected to said first register to receive said portion of the contents thereof, said control means operable to produce a control signal in response to a predetermined condition of said portion of the contents of said first register means, wherein said control signal is effective to activate said output register.
Claim 7
Dependent Claim
17 words
The combination recited in claim 1 wherein said ramp signal generating circuit produces a linear ramp signal.
Claim 8
Dependent Claim
79 words
The combination recited in claim 5 wherein said control means includes gate means connected to receive signals from said detector means, said gate means further connected to said comparator means to receive said signal representative of the relationship between signals produced by said ramp signal generator circuit and said voltage divider network, said gate means connected to supply a second control signal to said output register means when the representative signal from said comparator means achieves a predetermined status.
Claim 9
Dependent Claim
73 words
The combination recited in claim 7 wherein said control means includes: bistable means, gate means connected to receive a signal from said bistable means and to selectively supply signals to said output register, each of said bistable means and said gate means connected to receive the same clock signal which controls the operation thereof whereby said gate means selectively supplies a signal to said output register when said clock signal is supplied thereto.
Claim 10
Dependent Claim
37 words
The combination recited in claim 1 including means connecting said logic means to said ramp signal generating circuit to reset the operation thereof when the ramp signal achieves a predetermined level as determined by said comparator means.
Claim 11
Dependent Claim
29 words
The combination recited in claim 1 including converter means for complementing said portion of the contents of said first register means which is received by said first adder means.
Claim 12
Dependent Claim
62 words
The combination recited in claiM 1 wherein said logic means includes a plurality of bistable devices connected to said comparator means, said bistable devices producing output signals as a function of the signal produced by said comparator means, and gate means connected to said bistable means to receive output signals therefrom and to said recirculating register means to supply control signals thereto.
Claim 13
Dependent Claim
63 words
The combination recited in claim 11 including further bistable device connected to receive output signals from one of said plurality of bistable devices, said further bistable device connected to supply one output signal to said gate means, said further bistable device connected to supply the complement output signal to said first register means to reset said first register means to a predetermined condition.
Claim 14
Dependent Claim
182 words
The combination recited in claim 1 wherein said logic means includes means responsive to the output signal produced by said comparator means to produce control signals representative of different conditions of the signal produced by said ramp signal generating means, and means supplying a periodic signal to said logic means and to said recirculating means, said means responsive producing a first control signal when a periodic signal is supplied concurrent with a first condition of the signal produced by said ramp signal generating means, said first control signal being supplied to said first register to activate same, said means responsive producing a second control signal when a periodic signal is supplied concurrent with a second condition of the signal produced by said ramp signal generating means, said second control signal being supplied to said ramp generating means to inhibit operation thereof, to said second register to activate same, and reset control means connected to receive said second control signal from said means responsive and to supply a reset control signal to said first register means in response to the next periodic signal.
Claim 15
Dependent Claim
161 words
The combination recited in claim 1 wherein said output register produces an output signal which is a digital representation of the analog signal produced by said ramp signal generating means, said output register selectively energized by an output signal for said comparator means when the analog signal produced by said ramp signal generating means attains a predetermined condition whereby said output register stores a digital signal for periodic update, said first and second registers and said second adder interacting to produce said digital signals stored in said output register, said portion of the contents of said first register means comprising the most significant bits of the contents of said first register and comprising the digital signal to be stored in said output register, said first and second registers and said first adder interacting to produce a feedback path to vary the contents of said second register whereby the contents of said first register is varied by operation of said first adder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |