Patent US3886495A successfully refreshed from Google Patents.
US3886495A
Expired / Lapsed
US
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Uphole receiver for logging-while-drilling system
Assignee: Mobil Oil AS
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Filing: 1974-07-10
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Granted: 1975-05-27
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Expires: 1994-07-10
Abstract
Abstract In a system for logging-while-drilling, an improved uphole receiver correlates a signal representing a received acoustic signal with a reference signal derived from the received acoustic signal to produce a synchronously rectified signal whose polarity is representative of the phase states of the received acoustic signal. The synchronously rectified signal is applied to a first integrator which is sampled at the end of each bit time interval. The synchronously rectified signal is also applied to a second integrator which is sampled at the midpoint of each bit time interval. This sampled voltage represents the phase error in the bit clock pulses defining the bit time intervals. A synchronous inverter changes the polarity of the error signal so that the polarity is the same regardless of the direction of polarity change of the synchronously rectified signal during the integration period of the second integrator. The error signal is suppressed when there is no change in polarity in the synchronously rectified signal during the integration time of the second integrator.
Inventors
- 👤 James H Sexton
- 👤 Bobbie J Patton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:51
CPC Classifications
E; E21; E21B; E21B47/00; E21B47/12; E21B47/14; E21B47/18
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
176 words
In a system for logging-while-drilling wherein an acoustic signal is propagated through a liquid each from a downhole transmitter and the acoustic signal is modulated between two phase states in response to digitally coded data bits produced as a function of a downhole condition, and representation of each bit being propagated for a predetermined bit time interval, an improved receiving system for demodulating said acoustic waves comprising: means responsive to the acoustic signal for producing an output signal representative of the phase and frequency of said acoustic signal, a reference signal generator responsive to said output signal for producing a reference signal having one phase state, that being one of the phase states of said outpuT signal, a correlator, said output signal and said reference signal being applied to said correlator to produce a synchronously rectified signal whose polarity is representative of the phase states of said output signal, and means responsive to said reference signal for sampling said synchronously rectified signal to produce pulses representative of the generated bits and thus of the downhole condition.
Claim 2
Dependent Claim
176 words
In a system for logging-while-drilling wherein an acoustic signal is propagated through a liquid each from a downhole transmitter and the acoustic signal is modulated between two phase states in response to digitally coded data bits produced as a function of a downhole condition, and representation of each bit being propagated for a predetermined bit time interval, an improved receiving system for demodulating said acoustic waves comprising: means responsive to the acoustic signal for producing an output signal representative of the phase and frequency of said acoustic signal, a reference signal generator responsive to said output signal for producing a reference signal having one phase state, that being one of the phase states of said outpuT signal, a correlator, said output signal and said reference signal being applied to said correlator to produce a synchronously rectified signal whose polarity is representative of the phase states of said output signal, and means responsive to said reference signal for sampling said synchronously rectified signal to produce pulses representative of the generated bits and thus of the downhole condition.
Claim 3
Dependent Claim
53 words
The system recited in claim 1 further comprising: a first integrator, said synchronously rectified signal being applied to said first integrator, means for sampling said first integrator at the end of each of said bit time intervals, and means for resetting said integrator at the end of each of said bit time intervals.
Claim 4
Dependent Claim
84 words
The system recited in claim 2 further comprising: a second integrator, said synchronously rectified signal being applied to said second integrator, the integrating time of said second integrator being shifted by 1/2 bit time interval with respect to the integrating time of said first integrator, and means for sampling said second integrator at the midpoint of each of said bit time intervals, the sampled voltage being an error signal representing a phase error in the bit clock control pulses defining said bit time intervals.
Claim 5
Dependent Claim
79 words
The system recited in claim 2 further comprising: means for sensing the polarity of the sampled value of the output of the first integrator, and a synchronous inverter responsive to said means for sensing, said synchronous inverter changing the polarity of said error signal as necessary to make the polarity of the output of the synchronous inverter the same regardless of the direction of polarity change of the synchronously rectified signal during the integration period of said second integrator.
Claim 6
Dependent Claim
53 words
The system recited in claim 4 further comprising: means for sensing the absence of a polarity change of the synchronously rectified signal during the integration time of said second integrator, and means for suppressing said error signal when there is no change in this polarity in said integration time of said second integrator.
Claim 7
Dependent Claim
58 words
The system recited in claim 1 further comprising: frequency dividing means, said reference signal being applied to said frequency dividing means to divide it by the number of cycles in each bit of said output signal, the output of said frequency dividing means being a first set of bit clock control pulses which define said bit time intervals.
Claim 8
Dependent Claim
37 words
The system recited in claim 6 further comprising: means for changing the division ratio of said frequency dividing means so that said first set of bit clock control pulses match the number of cycles in each bit.
Claim 9
Dependent Claim
112 words
The system of claim 6 further comprising: a second integrator, said synchronously rectified signal being applied to said second integrator, the integrating time of said second integrator being shifted by 1/2 bit time interval with respect to the integrating time of said first integrator, and means for generating a second set of bit clock control pulses shifted 1/2 bit time interval from said first set, said second set of control pulses being applied to said second integrator to sample said second integrator at the midpoint of each of said bit time intervals, the sampled voltage being an error signal representing a phase error in said first set of bit clock control pulses.
Claim 10
Dependent Claim
39 words
The system recited in claim 6 further comprising: means for changing the phase of said bit clock control pulses so that said first set of bit clock control pulses coincide with the phase state transitions of the output signal.
Claim 11
Dependent Claim
40 words
The system recited in claim 6 further comprising: a sign change detector, the sampled output of said first integrator being applied to said sign change detector, and means responsive to said sign change detector for producing a bit value signal.
Claim 12
Dependent Claim
56 words
The system recited in claim 1 further comprising: a bandpass filter, an electRical signal representing said acoustic signal being applied to said bandpass filter to produce said output signal, said bandpass filter eliminating the harmonics of said acoustic signal so that said harmonics are not multiplied by the harmonics of said reference signal in said correlator.
Claim 13
Dependent Claim
27 words
The system recited in claim 1 wherein reference signal generator includes: a circuit for destroying the phase information of said output signal to produce a phase-free signal.
Claim 14
Dependent Claim
33 words
The system recited in claim 11 wherein said circuit is a squarer, said output signal being applied to said squarer to produce a squared signal that does not have said change in phase.
Claim 15
Dependent Claim
71 words
The system recited in claim 12 wherein said reference signal generator further includes a phase lock loop for producing a highly stable loop reference signal comprising: a variable frequency oscillator producing said loop reference signal, and a phase detector, said phase-free signal and said loop reference signal being applied to said phase detector to produce an error signal representing the error in phase between said loop reference and said squared signal.
Claim 16
Dependent Claim
77 words
The system recited in claim 14 wherein said phase lock loop includes a loop filter which generates a control signal comprising: means for producing an error signal component, means for integrating said error signal to produce an integral component, means for mixing said integral component and said error signal component, and means for changing the amplitudes of the mixed integral and error signal components to determine the noise band width and damping of said phase lock loop.
Claim 17
Dependent Claim
49 words
The system recited in claim 14 wherein said phase lock loop includes a loop filter which generates a control signal comprising: means for changing the bandwidth of said loop; and means for simultaneously changing the damping of said filter to maintain the optimum acquisition time consistent with said bandwidth.
Claim 18
Dependent Claim
19 words
The system recited in claim 16 wherein said damping factor is maintained at a constant value of about 0.5.
Claim 19
Dependent Claim
20 words
The system recited in claim 16 wherein said noise bandwidth is set at values of 1, 0.1 and 0.01 Hz.
Claim 20
Dependent Claim
68 words
The system recited in claim 14 wherein said phase lock loop includes a loop filter which generates a control signal comprising: means for producing an error signal component, means for integrating said error signal to produce an integral component, and means for adjusting the amplitude of the said error signal component and the said integral component to determine the noise bandwidth and damping of said phase lock loop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |