US3886461A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Missile radar doppler processing unit
Assignee: United States Department of the Navy
•
Filing: 1972-02-28
•
Granted: 1975-05-27
•
Expires: 1992-02-28
Abstract
Abstract A signal processor for an echo tracking system is disclosed. A circuit for storing zero signal crossings signal data is connected to read out circuitry to read out the stored signal in either real or compressed time. A controlled local oscillator processes the signals to pass through a single set of filters. The selection of operational mode is controlled by logic circuitry connected to receive the processed signal as well as command signals.
Inventors
- 👤 Lloyd J Hassencahl
- 👤 Leon Chernick
- 👤 James N Jonokuchi
- 👤 Joel Katz
- 👤 Richard L Wooley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:23
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/66; G01S13/72; G01S13/02; G01S13/50; G01S13/58; G01S13/585; G01S13/586
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
253 words
A data processing system comprising: amplifier means for increasing the power of an electrical signal having predetermined frequency characteristics; oscillator means for generating an electrical signal of a predetermined frequency; first mixer means connected to said amplifier means and to said oscillator means for producing an electrical signal having a frequency content including the sum and difference of said amplified signal and said oscillator frequency; time compression and playback means connected to said mixer means for the storage and accelerated reproduction of signals from said first mixer means; second mixer means effectively connected to said time compression and expansion means for receipt of the signal output therefrom; voltage controlled oscillator means connected to said second mixer means for supplying a heterodyne signal therefor; first detection means connected to said second mixer means for detection of electrical signals having predetermined characteristics; second detection means connected ahead of said first mixer means and to said second mixer means via first and second gate means respectively; logic circuit means connected to said first and second detection means for receipt of said detected output signals therefrom and connected gate means for control of signals applied to said second detector means in response to the detection of a predetermined signal by said first detection means; and timing control logic means including master clock means effectively connected to said time compression and playback means, said voltage controlled oscillator means, the gate means of said second detector means, and said logic circuit means for the timely and synchronous control thereof.
Claim 2
Dependent Claim
253 words
A data processing system comprising: amplifier means for increasing the power of an electrical signal having predetermined frequency characteristics; oscillator means for generating an electrical signal of a predetermined frequency; first mixer means connected to said amplifier means and to said oscillator means for producing an electrical signal having a frequency content including the sum and difference of said amplified signal and said oscillator frequency; time compression and playback means connected to said mixer means for the storage and accelerated reproduction of signals from said first mixer means; second mixer means effectively connected to said time compression and expansion means for receipt of the signal output therefrom; voltage controlled oscillator means connected to said second mixer means for supplying a heterodyne signal therefor; first detection means connected to said second mixer means for detection of electrical signals having predetermined characteristics; second detection means connected ahead of said first mixer means and to said second mixer means via first and second gate means respectively; logic circuit means connected to said first and second detection means for receipt of said detected output signals therefrom and connected gate means for control of signals applied to said second detector means in response to the detection of a predetermined signal by said first detection means; and timing control logic means including master clock means effectively connected to said time compression and playback means, said voltage controlled oscillator means, the gate means of said second detector means, and said logic circuit means for the timely and synchronous control thereof.
Claim 3
Dependent Claim
95 words
A data processing system according to claim 1 in which time compression and playback means includes: readin circuit means effectively connected to said first mixer means for processing signals applied thereto and connected to said timing control logic means for timely activation thereby; storage means connected to said readin circuit means for recording signals processed thereby and connected to said timing control logic means for timely activation thereby; and readout circuit means connected to said storage means for recovery of signals stored therein and connected to said timing control logic means for timely activation thereby.
Claim 4
Dependent Claim
34 words
A data processing system according to claim 2 in which the storage means includes two shift registers connected in a manner to be selectively placed in series circuit configuration or in parallel circuit configuration.
Claim 5
Dependent Claim
43 words
A data processing system according to claim 1 in which said effective connection between said voltage controlled oscillator and said timing control logic means includes a digital-to-analog converter circuit effective to cause said voltage controlled oscillator to sweep a predetermined range of frequencies.
Claim 6
Dependent Claim
76 words
A data processing system according to claim 1 in which said first detection means includes: a band pass filter connected to said second mixer means to filter the output thereof; envelope detector means connected to said band pass filter for producing output signals in response to amplitude variation in said filtered signal; and threshold amplifier means effectively connected to said envelope detector means for producing a signal when said detected output signal exceeds a predetermined value.
Claim 7
Dependent Claim
40 words
A data processing system according to claim 5 including digital-to-analog converter means connected between said threshold amplifier means and the aforesaid timing control logic means and effective to establish the predetermined threshold value in response to digital signals supplied thereto.
Claim 8
Dependent Claim
101 words
A data processing system according to claim 1 in which said second detector includes: a plurality of band pass filters connected in a parallel relationship and connected to said second mixer; first summing amplifier means connected to said plurality of band pass filter means for combining the outputs thereof into a single signal channel; a discriminator means effectively connected to said first summing amplifier means and connected to a phase detector; and a phase detector means effectively connected to said discriminator and connected to the aforesaid timing control logic means for detecting signals having predetermined relationship with regularly occurring timing signals.
Claim 9
Dependent Claim
32 words
A data processing system according to claim 7 further including discriminator means connected to one of said plurality of band pass filters for providing a second output from said second detector means.
Claim 10
Dependent Claim
41 words
A data processing system according to claim 8 further including second summing amplifier means connected to said discriminator means and effectively connected to the aforesaid first detector means, via the aforesaid logic circuit means, for providing a common output channel therefor.
Claim 11
Dependent Claim
62 words
A data processing system according to claim 7 further including: third detector means connected to one of said plurality of band pass filters for amplitude detection of the signals passed thereby; and threshold amplifier means effectively connected between the third detector means and the aforesaid logic circuit means for providing an output when signals from said third detector exceed a predetermined value.
References Cited (Backward Citations)
US3633173A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |