Method for production of p-channel field effect transistors and product resulting therefrom

Claim 2

A PROCESS FOR THE PRODUCTION OF A P-CHANNEL FIELD EFFECT TRANSISTOR WHICH INCLUDES FORMING A LAYER OF SILICON ON SPINEL SUBSTRATE, FORMING P+-SOURCE AND DRAIN REGIONS IN SAID SILICON LAYER WITH A GATE REGION THEREBETWEEN, FORMING AN INSULATING LAYER OVER SAID GATE REGION AND OVERLAPPING A PORTION OF EACH OF SAID SOURCE AND DRAIN REGIONS, FORMING ELECTRODES ON SAID INSULATING LAYER AND ON A PORTION OF EACH OF SAID SOURCE AND DRAIN REGIONS, AT LEAST ONE OF THE AFORESAID STEPS BEING CARRIED OUT AT A RELATIVELY HIGH TEMPERATURE, AND FINALLY ANNEALING SAID

Claim 3

A process as set forth in claim 1, wherein said annealing step is carried out at a temperature in the range of 300*-800*C for 10 to 60 minutes.

Claim 4

A process for the production of a p-channel field effect transistor which includes forming a layer of silicon on a spinel substrate, forming p -source and drain regions in said silicon layer with a gate region therebetween, forming an insulating layer over said gate region and overlapping a portion of each of said source and drain regions, at least one of the aforesaid steps being carried out at a relatively high temperature, annealing said substrate and said silicon layer in a hydrogen atmosphere after all of said high temperature steps have been terminated, and forming electrodes on said insulating layer and on a portion of each of said source and drain regions at a relatively low temperature.

Claim 5

A process for the production of a p-channel field effect transistor which includes forming a layer of silicon on a spinel substrate, forming p -source and drain regions in said silicon layer with a gate region therebetween, forming an insulating layer over said gate region and overlapping a portion of each of said source and drain regions, at least one of the aforesaid steps being carried out at a relatively high temperature, annealing said substrate and said silicon layer in a hydrogen atmosphere after all of said high temperature steps have been terminated, and forming electrodes on said insulating layer and on a portion of each of said source and drain regions at a relatively low temperature.

Claim 6

A process as set forth in calim 3, wherein said annealing step is carried out at a temperature in the range of 300*-800*C for 10 to 60 minutes.

Claim 7

A process as set forth in calim 3, wherein said annealing step is carried out at a temperature in the range of 300*-800*C for 10 to 60 minutes.

Claim 8

A process as set forth in claim 3, wherein said annealing step is carried out at a temperature in the range of 300*-800*C for 10 to 60 minutes, and in which the said annealing step is carried out before the application of material to form electrodes.

Claim 9

A process as set forth in claim 1, wherein said annealing step is carried out at a temperature in the range of 300*-800*C for 10 to 60 minutes, and wherein said annealing step is carried out after the application of material to form electrodes.

Claim 10

A process as set forth in claim 1, in which the annealing step is carried out at a temperature in the range of 300*-550*C for 10 to 60 minutes.

Claim 11

A process as set forth in claim 3, in which the annealing step is carried out at a temperature in the range of 300*-550*C for 10 to 60 minutes.

Claim 12

A process as set forth in claim 1, wherein the annealing step is carried out at a temperature in the range of 450*-500*C for 20 to 50 minutes.

Claim 13

A process as set forth in claim 3, wherein the annealing step is carried out at a temperature in the range of 450*-500*C for 20 to 50 minutes.

Claim 14

A process as set forth in claim 1, wherein said metal forming said electrodes forms a high temperature eutectic with silicon.

Claim 15

A process as set forth in claim 3, wherein said metal forming said electrodes forms a high temperature eutectic with silicon.

Claim 16

A process as set forth in claim 1, wherein said electrode material is polycrystalline silicon.

Claim 17

A process as set forth in claim 3, wherein said electrode material is polycrystalline silicon.

Claim 18

A process as set forth in claim 1, wherein said metal forming said electrodes is molybdenum.

Claim 19

A process as set forth in claim 3, wherein said metal forming said electrodes is molybdenum.

Claim 20

A process as set forth in claim 1, wherein said annealing step is carried out at a temperature above 500*C.

Claim 21

A process as set forth in claim 3, wherein said annealing step is carried out at a temperature above 500*C.

Claim 22

A process For the production of a p-channel field effect transistor in a semiconductor silicon layer on a spinel substrate, the substrate being formed of a Mg-Al material, the production of which requires at least one high temperature step which includes the step of annealing the substrate and the silicon in a hydrogen atmosphere after all of said high temperature steps have been completed.

Claim 23

A process For the production of a p-channel field effect transistor in a semiconductor silicon layer on a spinel substrate, the substrate being formed of a Mg-Al material, the production of which requires at least one high temperature step which includes the step of annealing the substrate and the silicon in a hydrogen atmosphere after all of said high temperature steps have been completed.

Claim 24

A process as set forth in claim 19, in which any aluminum incorporated in said silicon layer from said spinel substrate during the growth of said layer is reduced by a high temperature process effected prior to said annealing step.

Claim 25

A process for the production of a p-channel field effect transistor in a semiconductor layer comprising silicon on a spinel substrate, including the step of annealing the substrate and the silicon arranged thereon in a hydrogen atmosphere after all the high temperature processes required in the formation of the transistor have been completed.

Claim 26

A process for the production of a p-channel field effect transistor in a semiconductor layer comprising silicon on a spinel substrate, including the step of annealing the substrate and the silicon arranged thereon in a hydrogen atmosphere after all the high temperature processes required in the formation of the transistor have been completed.

Claim 27

A process for the production of a p-channel field effect transistor in a semiconductor silicon layer on a spinel substrate, the production of which requires at least one high temperature step which includes the step of annealing the substrate and the silicon after all of said high temperature steps have been completed.

Claim 28

A process for the production of a p-channel field effect transistor in a semiconductor silicon layer on a spinel substrate, the production of which requires at least one high temperature step which includes the step of annealing the substrate and the silicon after all of said high temperature steps have been completed.