Abstract This invention relates to a method and apparatus for processing yarn defect signals of a plurality of yarns on the on-line base. For this purpose and in the case of the signal processing apparatus according to this invention a large number of yarn defect signals are processed through a scanning device for signal sampling, means is provided for placing possible drop-out signals into respective provisional memories, and preferably in the form of a binary ''''1'''' from a binary ''''0'''' and for reading out the contents from the memories at the beginning the next succeeding sampling period and for further processing these read-out yarn defects signals, together with regular yarn defects signals under processing through regular samplings.
Inventors
👤 Tsugio Goto
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-24 15:30
CPC Classifications
D; D03; D03J; D03J1/00; D03J2700/00; D03J2700/06
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
220 words
An apparatus for processing defect signals from a plurality of yarns wherein said signals may be applied to a digital processor, said apparatus comprising: a. a plurality of sensor means, each sensor means associated with one of said yarns for detecting a defect in said yarns; b. a plurality of memory means, each of said memory means coupled to a coRresponding one of said sensor means for storing a defect signal produced by its corresponding sensor means; c. scanner means coupled to said plurality of memory means for cyclically sequentially sampling the signals stored in said memory means for subseqeunt output to said digital processor; and d. reset means for periodically resetting said memory means at the beginning of each sampling cycle; wherein each said memory means includes a thyristor, the anode thereof being coupled to said scanner means; a capacitor having one electrode connected to its corresponding sensor means; diode means coupled between the other electrode of said capacitor and the gate electrode of said thyristor, wherein said sensor means applies a pulse to the gate of said thyristor through said capacitor and diode means, turning said thyristor on and thereby changing the potential on the anode thereof when a defect signal is sensed by said sensor means; wherein said thyristor remains on until reset by said reset means.
Claim 2
Independent Claim
220 words
An apparatus for processing defect signals from a plurality of yarns wherein said signals may be applied to a digital processor, said apparatus comprising: a. a plurality of sensor means, each sensor means associated with one of said yarns for detecting a defect in said yarns; b. a plurality of memory means, each of said memory means coupled to a coRresponding one of said sensor means for storing a defect signal produced by its corresponding sensor means; c. scanner means coupled to said plurality of memory means for cyclically sequentially sampling the signals stored in said memory means for subseqeunt output to said digital processor; and d. reset means for periodically resetting said memory means at the beginning of each sampling cycle; wherein each said memory means includes a thyristor, the anode thereof being coupled to said scanner means; a capacitor having one electrode connected to its corresponding sensor means; diode means coupled between the other electrode of said capacitor and the gate electrode of said thyristor, wherein said sensor means applies a pulse to the gate of said thyristor through said capacitor and diode means, turning said thyristor on and thereby changing the potential on the anode thereof when a defect signal is sensed by said sensor means; wherein said thyristor remains on until reset by said reset means.
Claim 3
Dependent Claim
13 words
The apparatus of claim 1 wherein said sensor means is a capacitive sensor.
Claim 4
Dependent Claim
52 words
The apparatus of claim 1, wherein said scanner means includes normally open switch means associated with each memory means coupled to the anode of said thyristor wherein each said switch means is closed during the sampling of the corresponding memory means thereby coupling the anode of said thyristor to said processer means.
Claim 5
Dependent Claim
23 words
The apparatus of claim 1, wherein said reset means comprises means for grounding the anode of said thyristor thereby turning said thyristor off.