Patent US3885218A successfully refreshed from Google Patents.
US3885218A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Superheterodyne receiver having a digital indication of the received frequency
Assignee: Siemens AG
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Filing: 1973-04-06
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Granted: 1975-05-20
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Expires: 1993-04-06
Abstract
Abstract A superheterodyne receiver having a digital indication of the received frequency wherein a multi-stage counter serves for measuring the oscillations of a local oscillator by taking into consideration the frequency shift of its local oscillator frequency with respect to the received frequency. A correction circuit is controlled from the output of a counter stage to block the following counter stages during the occurrence of a number of output pulses of the first mentioned counter stage, which number is in proportion to the frequency offset.
Inventors
- 👤 Diethard Pfab
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:59
CPC Classifications
H; H03; H03J; H03J1/00; H03J1/02; H03J1/04; H03J1/045; H03J1/047; H03J1/048
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
148 words
A superheterodyne receiver which provides a digital indication of the receiving frequency by correcting the count of the local oscillator frequency to reflect the frequency offset of the local oscillator frequency with respect to the receiving frequency, said receiver comprising: a local oscillator; a multi-stage counter; means connecting said oscillator and said multi-stage counter and deriving a pulse train from the oscillations of said oscillator for operating said counter; means connected to said multi-stage counter for decoding and displaying the count thereof; and a correction circuit connected to first and second stages of any two adjacent stages of said multi-stage counter and operable from the output of said first stage to block said second stage for a predetermined number of output pulses from the first stage which is proportional to the frequency offset and unblock said second stage in response to detection of said predetermined number of pulses.
Claim 2
Dependent Claim
148 words
A superheterodyne receiver which provides a digital indication of the receiving frequency by correcting the count of the local oscillator frequency to reflect the frequency offset of the local oscillator frequency with respect to the receiving frequency, said receiver comprising: a local oscillator; a multi-stage counter; means connecting said oscillator and said multi-stage counter and deriving a pulse train from the oscillations of said oscillator for operating said counter; means connected to said multi-stage counter for decoding and displaying the count thereof; and a correction circuit connected to first and second stages of any two adjacent stages of said multi-stage counter and operable from the output of said first stage to block said second stage for a predetermined number of output pulses from the first stage which is proportional to the frequency offset and unblock said second stage in response to detection of said predetermined number of pulses.
Claim 3
Dependent Claim
39 words
A superheterodyne receiver according to claim 1, comprising a plurality of said correction circuits and wherein each of said correction circuits and the remainder of said receiver comprise cooperable plug-in connection links for easy replacement of a correction circuit.
Claim 4
Dependent Claim
38 words
A superheterodyne receiver according to claim 2, wherein said decoding and display means is connected to said multi-stage counter and is operable to display a count corresponding to said local oscillator frequency upon disconnection of said correction circuit.
Claim 5
Dependent Claim
60 words
A superheterodyne receiver according to claim 1, wherein said correction circuit includes a counting circuit connected to said first stage and having a counting capacity corresponding at least to a part of the frequency offset, a binary frequency divider connected to said counting circuit and connected to supply blocking and reset signals to said second stage of said multi-stage counter.
Claim 6
Dependent Claim
91 words
A superheterodyne receiver according to claim 4, comprising control means for applying a common reset and blocking signal to the stages of said multi-stage counter on each side of said second stage, gate means having a first input connected to said control means and a second input connected to the output of said frequency divider, a first output connected to said second stage of said multi-stage counter to provide blocking and reset signals, and a second output connected to said counting circuit and to said frequency divider to provide presetting thereof.
Claim 7
Dependent Claim
50 words
A superheterodyne receiver according to claim 5, comprising means for deriving a reset and blocking signal for said counting circuit including a gate having first and second inputs connected to respective ones of said first and second outputs of said gate means and an output connected to said counting circuit.
Claim 8
Dependent Claim
138 words
A superheterodyne receiver which provides a digital indication of the receiving frequency by correcting the count of the local oscillator frequency to reflect the frequency offset of the local oscillator frequency with respect to the receiving frequency, said receiver comprising: a local oscillator; a multistage counter; means connecting said oscillator and said multistage counter and deriving a pulse train from the oscillations of said oscillator for operating said counter; means connected to said multi-stage counter for Decoding and displaying the count thereof; and a correction circuit connected to first and second stages of any two adjacent stages of said multi-stage counter and operable in response to the occurrence of the first output pulse of said first stage to provide a number of counting pulses which is proportional to the frequency offset to subsequent stages of said multi-stage counter.
Claim 9
Dependent Claim
138 words
A superheterodyne receiver which provides a digital indication of the receiving frequency by correcting the count of the local oscillator frequency to reflect the frequency offset of the local oscillator frequency with respect to the receiving frequency, said receiver comprising: a local oscillator; a multistage counter; means connecting said oscillator and said multistage counter and deriving a pulse train from the oscillations of said oscillator for operating said counter; means connected to said multi-stage counter for Decoding and displaying the count thereof; and a correction circuit connected to first and second stages of any two adjacent stages of said multi-stage counter and operable in response to the occurrence of the first output pulse of said first stage to provide a number of counting pulses which is proportional to the frequency offset to subsequent stages of said multi-stage counter.
Claim 10
Dependent Claim
39 words
A superheterodyne receiver according to claim 7, wherein said correction circuit includes a start-stop generator which is operated to produce said number of pulses in response to said first output pulse of said first stage of said multi-stage counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-19 | 1978-11-18 | 1979-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-19 | 1982-11-18 | 1983-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-19 | 1986-11-18 | 1987-05-20 | $7700.00 | Window Closed / Lapsed |