Light dimmer

Claim 2

A dimmer circuit for decreasing the power provided by an A.C. Source of voltage to traffic lights comprising: a. switch means connected between said source and said traffic light; b. means connected to said source for providing a gating pulse each Nth cycle of said source; c. means for adjusting the time duration of said gating pulse to encompass n cycles where n is less than N and wherein each of the n cycles constitutes a whole wave form over 360*; and d. means for passing said gating pulse to said switch means to open said switch means every Nth cycle for the duration of n cycles whereby n/N of the power of said A.C. source is not passed to said traffic lights as a result of blockage of the n whole wave form cycles.

Claim 3

A dimmer circuit for dimming traffic lights wherein the lights are controlled by a logic circuit requiring a given source of alternating voltage for operation, and wherein the traffic lights are connected to said source through switches controlled by said logic circuit, said dimmer circuit including, in combination: a. input and output terminals for interposition between said source and said switches; b. detecting means connected to said input terminal to provide clock signals having a frequency determined by the frequency of alternating voltage; c. divider means connected to receive said clock signals and provide a control output pulse responsive to the reception of N clock signals, said output pulse having a time duration corresponding to the time for n clock signals to be received where n < OR = N; and d. a power switch means connected between said input terminal and output terminal and having a gate control terminal connected to receive said output pulse whereby said power switch is opened for a period corresponding to the width of said output pulse so that n/N of the power is not passed to said lights as a result of the blockage of n whole wave form cycles by said power switch.

Claim 4

A dimmer circuit for dimming traffic lights wherein the lights are controlled by a logic circuit requiring a given source of alternating voltage for operation, and wherein the traffic lights are connected to said source through switches controlled by said logic circuit, said dimmer circuit including, in combination: a. input and output terminals for interposition between said source and said switches; b. detecting means connected to said input terminal to provide clock signals having a frequency determined by the frequency of alternating voltage; c. divider means connected to receive said clock signals and provide a control output pulse responsive to the reception of N clock signals, said output pulse having a time duration corresponding to the time for n clock signals to be received where n < OR = N; and d. a power switch means connected between said input terminal and output terminal and having a gate control terminal connected to receive said output pulse whereby said power switch is opened for a period corresponding to the width of said output pulse so that n/N of the power is not passed to said lights as a result of the blockage of n whole wave form cycles by said power switch.

Claim 5

A circuit according to claim 2, in which N is four and in which means are provided to select a value of n 1, 2, or 3, whereby 25, 50, or 75 per cent of the power may be blocked from said lights.

Claim 6

A circuit according to claim 2, including photo detector means connected to said dimmer circuit for automatically actuating said dimmer circuit only when the ambient light falls below a given level.

Claim 7

A circuit according to claim 2, in which said detecting means includes a transistor having its base connected to said alternating voltage to provide clock signals having leading and trailing edges at the zero cross-over points of said alternating voltage and in which said divider means includes at least one flip flop circuit connected to receive said clock pulses.

Claim 8

A circuit according to claim 5 including an additional flip-flop circuit connected to the output of said first-mentioned flip-flop circuit; said divider means also including an ''''and'''' circuit having its input connected to receive the outputs from the first mentioned and additional flip-flop circuits; and an inverter circuit connected to the output of said ''''and'''' circuit, whereby said output pulse having a time duration can be selected from the output of said first mentioned flip-flop circuit, the output of said ''''and'''' circuit or the output from said inverter circuit.