US3885142A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Binary rate multipliers
Assignee: AT&T Inc
•
Filing: 1974-05-15
•
Granted: 1975-05-20
•
Expires: 1994-05-15
Abstract
Abstract An output binary rate vector is provided in response to a selected input number by generating a plurality of individual binary rate vectors substantially concurrently. Each of the individual vectors is generated in response to a different predetermined group of distinct adjacent bits of the input binary number. The individual vectors are generated by respective binary rate multiplier circuits, each of which includes a shift register and gating circuitry. The output binary rate vector is provided by serially extending the bits of the several individual vectors to an output terminal in a predetermined sequence.
Inventors
- 👤 William Herbert Ninke
- 👤 George Ray Ritchie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:05
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
136 words
In combination, circuit means operative in response to a selected input number for generating a hierarchy of individual binary rate unit vectors substantially concurrently, each of said unit vectors being generated in response to a respective associated bit group of said input number, the position of each of said unit vectors in said hierarchy corresponding to the positional significance in said input number of the bit group associated therewith, and means for successively repeating individual unit vectors of said hierarchy and for interposing each bit of each of said unit vectors, except the highest order unit vector, substantially halfway between successive repetitions of the entire next higher order unit vector of said hierarchy, said repeating and interposing means including an output terminal and means for extending selected bits of said unit vectors to said output terminal.
Claim 2
Dependent Claim
136 words
In combination, circuit means operative in response to a selected input number for generating a hierarchy of individual binary rate unit vectors substantially concurrently, each of said unit vectors being generated in response to a respective associated bit group of said input number, the position of each of said unit vectors in said hierarchy corresponding to the positional significance in said input number of the bit group associated therewith, and means for successively repeating individual unit vectors of said hierarchy and for interposing each bit of each of said unit vectors, except the highest order unit vector, substantially halfway between successive repetitions of the entire next higher order unit vector of said hierarchy, said repeating and interposing means including an output terminal and means for extending selected bits of said unit vectors to said output terminal.
Claim 3
Dependent Claim
65 words
The combination of claim 1 wherein said circuit means includes a plurality of binary rate multipliers each comprising a shift register and each operative in response to a respective one of said bit groups for generating a different one of said vectors, and wherein said extending means includes means for applying shift pulses selectively to said shift register of each of said binary rate multipliers.
Claim 4
Dependent Claim
23 words
The combination of claim 2 wherein said shift register in at least one of said binary rate multipliers comprises a recirculating shift register.
Claim 5
Dependent Claim
52 words
The combination of claim 2 wherein each of said binary rate multipliers further comprises means for loading each bit of a particular bit group into a respective predetermined number of stages of said shift register, said predetermined number corresponding to the positional significance of each said bit in said particular bit group.
Claim 6
Dependent Claim
38 words
The combination of claim 2 wherein said extending means further includes AND circuit means operative in response to said shift pulses for extending the bits of said unit vectors from said binary rate multipliers to said output terminal.
Claim 7
Dependent Claim
82 words
A binary rate multiplier comprising first circuit means responsive to a first bit group of a selected input number for providing a corresponding first binary rate vector in parallel form, second circuit means responsive to a second bit group of said input number for providing a corresponding second binary rate vector in parallel form, an output terminal, and means for repetitively extending the whole of said first vector to said output terminal in alternation with successive individual bits of said second vector.
Claim 8
Dependent Claim
82 words
A binary rate multiplier comprising first circuit means responsive to a first bit group of a selected input number for providing a corresponding first binary rate vector in parallel form, second circuit means responsive to a second bit group of said input number for providing a corresponding second binary rate vector in parallel form, an output terminal, and means for repetitively extending the whole of said first vector to said output terminal in alternation with successive individual bits of said second vector.
Claim 9
Dependent Claim
41 words
The binary rate multiplier of claim 6 wherein said first circuit means includes a first shift register, and first means for generating said first binary rate vector and for loading the bits thereof into respective stages of said first shift register.
Claim 10
Dependent Claim
54 words
The binary rate multiplier of claim 7 wherein said first generating and loading means includes means for loading each bit of said first bit group into a respective predetermined number of stages of said first shift register, said predetermined number corresponding to the positional significance of each said bit in said first bit group.
Claim 11
Dependent Claim
22 words
The binary rate multiplier of claim 7 wherein said first shift register includes means for recirculating the bits of said first vector.
Claim 12
Dependent Claim
70 words
The binary rate multiplier of claim 7 wherein said second circuit means includes a second shift register and second means for generating said second binary rate vector and for loading the bits thereof into respective stages of said second shift register, and wherein said extending means includes means for shifting the bits of said first and second vectors to said output terminal from said first and second shift registers, respectively.
Claim 13
Dependent Claim
112 words
A binary rate multiplier comprising first and second shift registers, means for loadng into said first and second shift registers first and second binary rate vectors respectively, said first and second vectors respectively corresponding to first and second bit groups of a selected input number, the bits of said second bit group being of lower significance in said input number than those of sid first group, an output terminal, first means operative for shifting the whole of said first vector to said output terminal, a second means operative for shifting single successive bits of said second vector to said output terminal, and means for alternately operating said first and second shifting means.
Claim 14
Dependent Claim
112 words
A binary rate multiplier comprising first and second shift registers, means for loadng into said first and second shift registers first and second binary rate vectors respectively, said first and second vectors respectively corresponding to first and second bit groups of a selected input number, the bits of said second bit group being of lower significance in said input number than those of sid first group, an output terminal, first means operative for shifting the whole of said first vector to said output terminal, a second means operative for shifting single successive bits of said second vector to said output terminal, and means for alternately operating said first and second shifting means.
Claim 15
Dependent Claim
56 words
The binary rate multiplier of claim 11 wherein said loading means includes means for loading each bit of said first and second bit groups into a respective predetermined number of stages of said first and second shift registers, respectively, said predetermined number corresponding to the positional significance of said each bit in the bit group thereof.
Claim 16
Dependent Claim
34 words
The binary rate multiplier of claim 12 further comprising means operative in response to the operation of said first shifting means for recirculating the bits of said first vector in said first shift register.
Claim 17
Dependent Claim
79 words
The binary rate multiplier of claim 13 wherein said first and second shifting means include OR circuit means and respective first and second AND circuit means, said first and second AND circuit means being operative in response to said first and second shifting means, respectively, for extending vector bits previously loaded into said first and second shift registers to respective inputs of said OR circuits means, the output of said OR circuit means being connected to said output terminal.
Claim 18
Independent Claim
144 words
A method of generating a binary rate vector in response to a predetermined input number, said method comprising the steps of, generating a hierarchy of individual binary rate unit vectors substantially concurrently, each of said unit vectors being generated in response to a respective associated one of a plurality of bit groups within said input number, the position of each one of said unit vectors in said hierarchy corresponding to the positional significance in said input number of the bit group associated therewith, and successively repeating particular unit vectors of said hierarchy and interposIng each bit of each of said unit vectors, except the highest order unit vector, substantially halfway between successive repetitions of the entire next higher order unit vector of said hierarchy, said repeating and interposing step including the step of extending selected bits of said unit vectors to an output terminal.
Claim 19
Independent Claim
144 words
A method of generating a binary rate vector in response to a predetermined input number, said method comprising the steps of, generating a hierarchy of individual binary rate unit vectors substantially concurrently, each of said unit vectors being generated in response to a respective associated one of a plurality of bit groups within said input number, the position of each one of said unit vectors in said hierarchy corresponding to the positional significance in said input number of the bit group associated therewith, and successively repeating particular unit vectors of said hierarchy and interposIng each bit of each of said unit vectors, except the highest order unit vector, substantially halfway between successive repetitions of the entire next higher order unit vector of said hierarchy, said repeating and interposing step including the step of extending selected bits of said unit vectors to an output terminal.
Claim 20
Dependent Claim
61 words
The method of claim 15 wherein said generating step includes the step of loading each bit of each one of said bit groups into a respective predetermined number of stages of a shift register associated with said one of said bit groups, said predetermined number corresponding to the positional significance of said each bit in said one of said bit groups.
Claim 21
Dependent Claim
27 words
The method of claim 16 wherein said extending step includes the step of applying shift pulses to the shift register associated with each of said bit groups.
Claim 22
Independent Claim
108 words
A method for generating a binary rate vector in response to a predetermined input number, said method comprising the steps of, generating a first binary rate vector in parallel form, said first vector corresponding to a first bit group of said input number, generating a second binary rate vector in parallel form, said second vector corresponding to a second bit group of said input number, the bits of said second group being of lower significance in said input number than those of said first group, and repetitively extending the whole of said first vector to an output terminal in alternation with successive individual bits of said second vector.
Claim 23
Independent Claim
108 words
A method for generating a binary rate vector in response to a predetermined input number, said method comprising the steps of, generating a first binary rate vector in parallel form, said first vector corresponding to a first bit group of said input number, generating a second binary rate vector in parallel form, said second vector corresponding to a second bit group of said input number, the bits of said second group being of lower significance in said input number than those of said first group, and repetitively extending the whole of said first vector to an output terminal in alternation with successive individual bits of said second vector.
Claim 24
Independent Claim
133 words
A method of generating a binary rate vector in response to a predetermined input number, said method comprising the steps of, generating at least first, second and third binary rate vectors in response to first, second and third bit groups of said input number, said bit groups being of descending positional significance in said input number in the order named, the bits of each one of said first, second and third vectors being generated substantially concurrently with each other bit of the same vector, and repetitively applying the whole of said first vector to an output terminal in alternation with successive individual bits taken from a predetermined sequence of bits from said second and third vectors, the bits of said third vector alternating in said sequence with the whole of said second vector.
Claim 25
Independent Claim
133 words
A method of generating a binary rate vector in response to a predetermined input number, said method comprising the steps of, generating at least first, second and third binary rate vectors in response to first, second and third bit groups of said input number, said bit groups being of descending positional significance in said input number in the order named, the bits of each one of said first, second and third vectors being generated substantially concurrently with each other bit of the same vector, and repetitively applying the whole of said first vector to an output terminal in alternation with successive individual bits taken from a predetermined sequence of bits from said second and third vectors, the bits of said third vector alternating in said sequence with the whole of said second vector.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-19 | 1978-11-18 | 1979-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-19 | 1982-11-18 | 1983-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-19 | 1986-11-18 | 1987-05-20 | $7700.00 | Window Closed / Lapsed |