Address generator for rotating data storage devices

Claim 2

In a data storage system adapted to organize the storage of data into individually addressable segments of tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency, said system including means for generating a coded zone selecting signal to select a particular zone for access; an address generator for providing a current segment address which comprises: means directly assoicated with the memory store for generating a memory store clock signal having a predetermined frequency responsive to the speed of rotation of the memory store wherein the frequency of said memory store clock signal may be higher than all of said zone frequencies, lower than all of said zone frequencies, intermediate any two of said zone frequencies, or substantially equal to any one of said zone frequencies, as desired; circuit means for deriving a plurality of read/write clock signals from said memory store clock signal, each one of said read/write clock signals comprising a pulse train having a distinct frequency substantially equal to a different one of said zone frequencies whereby each of said read/write clock signals is independently associated with a distinct one of said zones for synchronizing the recording of data in and retrieving of data from segments in the assoicated zone first counting circuit means for counting the pulses of a read/write clock signal, said first counting circuit means having a modulo equal to the number of bits storable in a segment and generating an output pulse each time the number of read/write clock signal pulses counted therein reaches said modulo; second counting circuit means for accumulating a current segment address therein by counting the output pulses of said first counting circuit means, and means generating a mark pulse each time the memory store completes a revolution for resetting said first and second counting circuit means in response to each occurrence of said mark pulse.

Claim 3

An address generator as recited in claim 1 wherein said circuit means for deriving a plurality of read/write clock signals comprises means for generating all of said read/write clock signals simultaneously.

Claim 4

An address generator as recited in claim 2 wherein said first counting circuit means comprises a plurality of individual bit counting circuits, each of said bit counting circuits having a distinct one of said read/write clock signals coupled as an input thereto.

Claim 5

An address generator as recited in claim 3 wherein said second counting circuit means comprises a plurality of individual segment counting circuits, each of said segment counting circuits having the output pulses of a bit counting circuit coupled as an input thereto for causing each of said segment counting circuits to accumulate a current segment address therein applicable to a distinct one of said zones.

Claim 6

An address generator as recited in claim 2 which comprises means for selecting a particular one of the simultaneously generated plurality of read/write clock signals for use in synchronizing the recording and retrieving of data, said selecting means having the zone selecting signal coupled thereto for effecting the selection of that read/write clock signal having its frequency substantially equal to the zone frequency characterizing the selected zone.

Claim 7

An address generator as recited in claim 5 wherein said first counting circuit means comprises a bit counting circuit coupled to receive said selected read/write clock signal; and wherein said second counting circuit means comprises a segment counting circuit coupled to receive the output pulses of said bit counting circuit.

Claim 8

An address generator as recited in claim 5 which comprises means for inhibiting access to the memory store upon the occurrence of a change in said zone selecting signal until a mark pulse is generated.

Claim 9

An address generator as recited in claim 1 wherein said circuit means for deriving a plurality of read/write clock signals comprises: a frequency multiplying circuit having a predetermined multiplication factor, said frequency multiplying circuit operating on said memory store clock signal to produce a reference clock signal wherein the frequency of the reference clock signal may be any frequency higher than that of the memory store clock signal, as desired; and a frequency divider circuit having a division factor capable of being varied for operating on said reference clock signal to produce a selected one of said plurality of read/write clock signals, said frequency divider circuit having the zone selecting signal coupled thereto for determining said division factor.

Claim 10

An address generator as recited in claim 8 wherein said first counting circuit means comprises a bit counting circuit coupled to receive said selected read/write clock signal; and wherein said second counting circuit means comprises a segment counting circuit coupled to receive the output pulses of said bit counting circuit.

Claim 11

An address generator as recited in claim 8 which comprises means for inhibiting access to the memory store upon the occurrence of a change in said zone selecting signal until a mark pulse is generated.

Claim 12

In a data storage system adapted to store data in tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency; the combination for generating read/write clock signals for synchronizing said recording and retrieving of data which comprises: means directly associated with the memory store for generating a memory store clock signal having a predetermined frequency responsive to the speed of rotation of the memory store wherein the frequency of said memory store clock signal may be higher than all of said zone frequencies, lower than all of said zone frequencies, intermeDiate any two of said zones frequencies, or substantially equal to any one of said zone frequencies, as desired; and circuit means for deriving a plurality of read/write clock signals from said memory store clock signal, each one of said read/write clock signals comprising a pulse train having a distinct frequency substantially equal to a different one of said zone frequencies whereby each of said read/write clock signals is independently associated with a distinct one of said zones for synchronizing the recording of data in and retrieving of data from segments in the associated zone.

Claim 13

In a data storage system adapted to store data in tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency; the combination for generating read/write clock signals for synchronizing said recording and retrieving of data which comprises: means directly associated with the memory store for generating a memory store clock signal having a predetermined frequency responsive to the speed of rotation of the memory store wherein the frequency of said memory store clock signal may be higher than all of said zone frequencies, lower than all of said zone frequencies, intermeDiate any two of said zones frequencies, or substantially equal to any one of said zone frequencies, as desired; and circuit means for deriving a plurality of read/write clock signals from said memory store clock signal, each one of said read/write clock signals comprising a pulse train having a distinct frequency substantially equal to a different one of said zone frequencies whereby each of said read/write clock signals is independently associated with a distinct one of said zones for synchronizing the recording of data in and retrieving of data from segments in the associated zone.

Claim 14

The combination as recited in claim 11 wherein said circuit means comprises at least one frequency divider circuit having said memory store clock signal as an input and a read/write clock signal as an output, said frequency divider circuit having a division factor selected to cause the frequency of the read/write clock signal output thereby to be substantially equal to one of said zone frequencies.

Claim 15

The combination as recited in claim 11 wherein said circuit means comprises a frequency multiplying circuit having a predetermined multiplication factor, said frequency multiplying circuit operating on said memory store clock signal to produce a reference clock signal wherein the frequency of the reference clock signal may be any frequency higher than that of the memory store clock signal, as desired.

Claim 16

The combination as recited in claim 13 wherein said predetermined multiplication factor is selected to cause the frequency of the reference clock signal to be substantially equal to one of said zone frequencies.

Claim 17

The combination as recited in claim 13 wherein said circuit means comprises at least one frequency divider circuit having said reference clock signal as an input and a read/write clock signal as an input, said frequency divider circuit having a division factor selected to cause the frequency of the read/write clock signal output thereby to be substantially equal to one of said zone frequencies.

Claim 18

The combination as recited in claim 15 wherein said predetermined division factor is an integer.

Claim 19

In a data storage system adapted to store data in tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency, said system including means for generating a coded zone selected signal to select a particular zone for access; the combination for generating read/write clock signals for synchronizing said recording and retrieving of data which comprises: means for generating a first clock signal having a predetermined frequency responsive to the speed of rotation of the memory store wherein the frequency of said first clock signal may be higher than all of said zone frequencies, intermediate any two of said zone frequencies; or substantially equal to one of said zone frequencies, as desired; and a frequency divider circuit having a division factor capable of being varied for operating on said first clock signal to produce a read/write clock signal having a frequency substantially equal to one of said zone frequencies, said frequency divider circuit having the zone selecting signal coupled thereto for determining said division factor.

Claim 20

In a data storage system adapted to store data in tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency, said system including means for generating a coded zone selected signal to select a particular zone for access; the combination for generating read/write clock signals for synchronizing said recording and retrieving of data which comprises: means for generating a first clock signal having a predetermined frequency responsive to the speed of rotation of the memory store wherein the frequency of said first clock signal may be higher than all of said zone frequencies, intermediate any two of said zone frequencies; or substantially equal to one of said zone frequencies, as desired; and a frequency divider circuit having a division factor capable of being varied for operating on said first clock signal to produce a read/write clock signal having a frequency substantially equal to one of said zone frequencies, said frequency divider circuit having the zone selecting signal coupled thereto for determining said division factor.

Claim 21

In a data storage system adapted to organize the storage of data into individually addressable segments of tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency, said system including means for generating a coded zone selecting signal to select a particular zone for access and further including means for generating at Least one coded segment length selecting signal to select the number of bits to be stored in a segment; an address generator for providing a current segment address which comprises: means for generating a plurality of read/write clock signals, each one of said read/write clock signals comprising a pulse train having a distinct frequency substantially equal to a different one of said zone frequencies and responsive to the speed of rotation of the memory store whereby each of said read/write clock signals is independently associated with a distinct one of said zones for synchronizing the recording of data in and retrieving of data from segments in the associated zone; first counting circuit means for counting the pulses of a read/write clock signal, said first counting circuit means having a variable modulo and generating an output pulse each time the number of read/write clock signal pulses counted therein reaches said modulo, said first counting means further having a segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; second counting circuit means for accumulating a current segment address therein by counting the output pulses of said first counting circuit means; and means generating a mark pulse each time the memory store completes a revolution for resetting said first and second counting circuit means in response to each occurrence of said mark pulse.

Claim 22

In a data storage system adapted to organize the storage of data into individually addressable segments of tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency, said system including means for generating a coded zone selecting signal to select a particular zone for access and further including means for generating at Least one coded segment length selecting signal to select the number of bits to be stored in a segment; an address generator for providing a current segment address which comprises: means for generating a plurality of read/write clock signals, each one of said read/write clock signals comprising a pulse train having a distinct frequency substantially equal to a different one of said zone frequencies and responsive to the speed of rotation of the memory store whereby each of said read/write clock signals is independently associated with a distinct one of said zones for synchronizing the recording of data in and retrieving of data from segments in the associated zone; first counting circuit means for counting the pulses of a read/write clock signal, said first counting circuit means having a variable modulo and generating an output pulse each time the number of read/write clock signal pulses counted therein reaches said modulo, said first counting means further having a segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; second counting circuit means for accumulating a current segment address therein by counting the output pulses of said first counting circuit means; and means generating a mark pulse each time the memory store completes a revolution for resetting said first and second counting circuit means in response to each occurrence of said mark pulse.

Claim 23

An address generator as recited in claim 18 wherein said means for generating a plurality of read/write clock signals comprises means for generating all of said read/write clock signals simultaneously.

Claim 24

An address generator as recited in claim 19 wherein said first counting circuit means comprises a plurality of individual variable modulo bit counting circuits, each of said variable modulo bit counting circuits having a distinct one of said read/write clock signals coupled as a first input thereto and each having a segment length selecting signal coupled as a second input thereto.

Claim 25

An address generator as recited in claim 20 wherein said second counting circuit means comprises a plurality of individual segment counting circuits, each of said segment counting circuits having the output pulses of a bit counting circuit coupled as an input thereto for causing each of said segment counting circuits to accumulate a current segment address therein applicable to a distinct one of said zones.

Claim 26

An address generator as recited in claim 19 which comprises means for selecting a particular one of the simultaneously generated plurality of read/write clock signals for use in synchronizing the recording and retrieving of data, said selecting means having the zone selecting signal coupled thereto for effecting the selection of that read/write clock signal having its frequency substantially equal to the zone frequency characterizing the selected zone.

Claim 27

An address generator as recited in claim 22 wherein said first counting circuit means comprises a variable modulo bit counting circuit coupled to receive said selected read/write clock signal as a first input thereto and coupled to receive a segment length selecting signal as a second input thereto; and wherein said second counting circuit means comprises a segment counting circuit coupled to receive the output pulses of said variable modulo bit counting circuit.

Claim 28

An address generator as recited in claim 18 which comprises means for inhibiting access to the memory store upon the occurrence of a change in said zone selecting signal until said mark pulse is generated.

Claim 29

An address generator as recited in claim 18 wherein said means for generating a plurality of read/write clock signals comprises: a frequency multiplying circuit having a predetermined multiplication factor, said frequency multiplying circuit operating on a memory store clock signal to produce a reference clock signal wherein the frequency of the memory store clock signal may be higher Than all of said zone frequencies, lower than all of said zone frequencies, intermediate any two of said zone frequencies, or substantially equal to any one of said zone frequencies, as desired, and wherein the frequency of the reference clock signal may be any frequency higher than that of the memory store clock signal, as desired, and a frequency divider circuit having a division factor capable of being varied for operating on said reference clock signal to produce a selected one of said plurality of read/write clock signals, said frequency divider circuit having the zone selecting signal coupled thereto for determining said division factor.

Claim 30

An address generator as recited in claim 25 wherein said first counting circuit means comprises a variable modulo bit counting circuit coupled to receive said selected read/write clock signal as a first input thereto and coupled to receive a segment length selecting signal as a second input thereto; and wherein said second counting circuit means comprises a segment counting circuit coupled to receive the output pulses of said variable modulo bit counting circuit.

Claim 31

In a data storage system adapted to organize the storage of data into individually addressable segments of varying length on tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency, said system including: means for generating a coded zone selecting signal to select a particular zone for access; means for generating at least one coded segment length selecting signal to select the number of bits to be stored in a segment; and means for generating a track selecting signal to select a particular track for access; an address generator for providing a current segment address which comprises: means for generating a plurality of read/write clock signals, each one of said read/write clock signals comprising a pulse train having a distinct frequency substantially equal to a different one of said zone frequencies and responsive to the speed of rotation of the memory store whereby each of said read/write clock signals is independently associated with a distinct one of said zones for synchronizing the recording of data in and retrieving of data from segments in the associated zone; first counting circuit means for counting the pulses of a read/write clock signal, said first counting circuit means having a variable modulo and generating an output pulse each time the number of read/write clock signal pulses counted therein reaches said modulo, said first counting means further having a segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; second counting circuit means for accumulating a current segment address therein by counting the output pulses of said first counting circuit means; means generating a mark pulse each time the memory store completes a revolution for resetting said first and second counting circuit means in response to each occurrence of said mark pulse; means for inhibiting access to the memory store upon the occurrence of a change in said zone selecting signal until said mark pulse is generated; and means for inhibiting access to the memory store upon the occurrence of a change in said track selecting signal until said mark pulse is generated.

Claim 32

In a data storage system adapted to organize the storage of data into individually addressable segments of varying length on tracks on a rotating memory store, the tracks being grouped into a plurality of zones wherein each zone is characterized by a distinct predetermined zone frequency for recording and retrieving data, the zone frequency characterizing each one of said zones being a frequency different from any other zone frequency, said system including: means for generating a coded zone selecting signal to select a particular zone for access; means for generating at least one coded segment length selecting signal to select the number of bits to be stored in a segment; and means for generating a track selecting signal to select a particular track for access; an address generator for providing a current segment address which comprises: means for generating a plurality of read/write clock signals, each one of said read/write clock signals comprising a pulse train having a distinct frequency substantially equal to a different one of said zone frequencies and responsive to the speed of rotation of the memory store whereby each of said read/write clock signals is independently associated with a distinct one of said zones for synchronizing the recording of data in and retrieving of data from segments in the associated zone; first counting circuit means for counting the pulses of a read/write clock signal, said first counting circuit means having a variable modulo and generating an output pulse each time the number of read/write clock signal pulses counted therein reaches said modulo, said first counting means further having a segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; second counting circuit means for accumulating a current segment address therein by counting the output pulses of said first counting circuit means; means generating a mark pulse each time the memory store completes a revolution for resetting said first and second counting circuit means in response to each occurrence of said mark pulse; means for inhibiting access to the memory store upon the occurrence of a change in said zone selecting signal until said mark pulse is generated; and means for inhibiting access to the memory store upon the occurrence of a change in said track selecting signal until said mark pulse is generated.

Claim 33

An address generator as recited in claim 27 wherein said means for generating a plurality of read/write clock signals comprises means for generating all of said read/write clock signals simultaneously.

Claim 34

An address generator as recited in claim 28 wherein said first counting circuit means comprises a plurality of individual variable modulo bit counting circuits, each of said variable modulo bit counting circuits having a distinct one of said read/writE clock signals coupled as a first input thereto and each having a segment length selecting signal coupled as a second input thereto.

Claim 35

An address generator as recited in claim 29 wherein said second counting circuit means comprises a plurality of individual segment counting circuits, each of said segment counting circuits having the output pulses of a bit counting circuit coupled as an input thereto for causing each of said segment counting circuits to accumulate a current segment address therein applicable to a distinct one of said zones.

Claim 36

An address generator as recited in claim 28 which comprises means for selecting a particular one of the simultaneously generated plurality of read/write clock signals for use in synchronizing the recording and retrieving of data, said selecting means having the zone selecting signal coupled thereto for effecting the selection of that read/write clock signal having its frequency substantially equal to the zone frequency characterizing the selected zone.

Claim 37

An address generator as recited in claim 31 wherein said first counting circuit means comprises a variable modulo bit counting circuit coupled to receive said selected read/write clock signal as a first input thereto and coupled to receive a segment length selecting signal as a second input thereto; and wherein said second counting circuit means comprises a segment counting circuit coupled to receive the output pulses of said variable modulo bit counting circuit.

Claim 38

An address generator as recited in claim 27 wherein said means for generating a plurality of read/write clock signals comprises: a frequency multiplying circuit having a predetermined multiplication factor, said frequency multiplying circuit operating on a memory store clock signal to produce a reference clock signal wherein the frequency of the memory store clock signal may be higher than all of said zone frequencies, lower than all of said zone frequencies, intermediate any two of said zone frequencies, or substantially equal to any one of said zone frequencies, as desired, and wherein the frequency of the reference clock signal may be any frequency higher than that of the memory store clock signal, as desired; and a frequency divider circuit having a division factor capable of being varied for operating on said reference clock signal to produce a selected one of said plurality of read/write clock signals, said frequency divider circuit having the zone selecting signal coupled thereto for determining said division factor.

Claim 39

An address generator as recited in claim 33 wherein said first counting circuit means comprises a variable modulo bit counting circuit coupled to receive said selected read/write clock signal as a first input thereto and coupled to receive a segment length selecting signal as a second input thereto; and wherein said second counting circuit means comprises a segment counting circuit coupled to receive the output pulses of said variable modulo bit counting circuit.

Claim 40

In a data storage system adapted to organize the storage of data into individually addressable segments of tracks on a rotating memory store, said system comprising means for generating a coded segment length selecting signal to select the number of bits to be stored in a segment; an address generator which comprises: means for generating a read/write clock signal comprising a pulse train having a predetermined frequency responsive to the speed of rotation of the memory store for synchronizing the transfer of information to and from said segments; a variable modulo bit counting circuit coupled to count the pulses of said read/write clock signal and generating an output pulse each time the number of read/write clock signal pulses counted therein reaches said modulo, said variable modulo bit counting circuit further having the segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; a segment counting circuit for accuMulating a current segment address therein coupled to count the output pulses of said bit counting circuit; and means generating a mark pulse each time the memory store completes a revolution for resetting said bit counting circuit and said segment counting circuit in response to each occurrence of said mark pulse.

Claim 41

In a data storage system adapted to organize the storage of data into individually addressable segments of tracks on a rotating memory store, said system comprising means for generating a coded segment length selecting signal to select the number of bits to be stored in a segment; an address generator which comprises: means for generating a read/write clock signal comprising a pulse train having a predetermined frequency responsive to the speed of rotation of the memory store for synchronizing the transfer of information to and from said segments; a variable modulo bit counting circuit coupled to count the pulses of said read/write clock signal and generating an output pulse each time the number of read/write clock signal pulses counted therein reaches said modulo, said variable modulo bit counting circuit further having the segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; a segment counting circuit for accuMulating a current segment address therein coupled to count the output pulses of said bit counting circuit; and means generating a mark pulse each time the memory store completes a revolution for resetting said bit counting circuit and said segment counting circuit in response to each occurrence of said mark pulse.

Claim 42

In a data storage system adapted to organize the storage of data into individually addressable segments of varying length on tracks on a rotating memory store, said system comprising means for generating a coded segment length selecting signal to select the number of bits to be stored in a segment and means for generating a track selecting signal to select a particular track for access; an address generator which comprises: means for generating a read/write clock signal comprising a pulse train having a predetermined frequency responsive to the speed of rotation of the memory store for synchronizing the transfer of information to and from said segments; a variable modulo bit counting circuit coupled to count the pulses of said read/write clock signal and generating an output pulse each time the number of read/write clock signal pulses conted therein reaches said modulo, said variable modulo bit counting circuit further having the segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; a segment counting circuit for accumulating a current segment address therein coupled to count the output pulses of said bit counting circuit; means generating a mark pulse each time the memory store completes a revolution for resetting said bit counting circuit and said segment counting circuit in response to each occurrence of said mark pulse; and means for inhibiting access to the memory store upon the occurrence of a change in said track selecting signal until said mark pulse is generated.

Claim 43

In a data storage system adapted to organize the storage of data into individually addressable segments of varying length on tracks on a rotating memory store, said system comprising means for generating a coded segment length selecting signal to select the number of bits to be stored in a segment and means for generating a track selecting signal to select a particular track for access; an address generator which comprises: means for generating a read/write clock signal comprising a pulse train having a predetermined frequency responsive to the speed of rotation of the memory store for synchronizing the transfer of information to and from said segments; a variable modulo bit counting circuit coupled to count the pulses of said read/write clock signal and generating an output pulse each time the number of read/write clock signal pulses conted therein reaches said modulo, said variable modulo bit counting circuit further having the segment length selecting signal coupled thereto to set said modulo equal to the number of bits storable in a segment; a segment counting circuit for accumulating a current segment address therein coupled to count the output pulses of said bit counting circuit; means generating a mark pulse each time the memory store completes a revolution for resetting said bit counting circuit and said segment counting circuit in response to each occurrence of said mark pulse; and means for inhibiting access to the memory store upon the occurrence of a change in said track selecting signal until said mark pulse is generated.