US3883372A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making a planar graded channel MOS transistor
Assignee: Amtel Corp
•
Filing: 1973-07-11
•
Granted: 1975-05-13
•
Expires: 1993-07-11
Abstract
Abstract The method of fabrication of a planar narrow channel metal oxide semiconductor field effect transistor (MOSFET) by a double diffusion through a self-aligned silicon gate wherein a first type dopant is diffused into the same self-aligned window of the source diffusion already diffused with a second type dopant. The diffused source and drains are self-aligned by means of the silicon gate, thus permitting narrow gate lengths. The diffusion profile is such that the impurity concentration near the source is higher than that near the drain. When a reverse bias is applied between, for example, an n-type drain and a p-type diffused region, the depletion layer cannot widen as much toward the source as a uniform channel because of the impurity concentration profile. Thus a narrow channel length can be used withoout drain-source punch-through at low voltages. Meanwhile, the self-aligned silicon gate permits a close spacing between the source and drain contacts, thus reducing the feedback capacitance between the drain and the gate.
Inventors
- 👤 Hung Chang Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:46
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; Y; Y10; Y10S; Y10S148/00; Y10S148/053; Y10S148/106; Y10S148/167
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
412 words
A METHOD OF MAKING A PLANAR METAL OXIDE SEMICONDUCTOR FIELD EFFECT DEVICE HAVING A RELATIVELY NARROW CHANNEL REGION AND A SILICON, GATE, WHEREIN THE IMPROVEMENT COMPRISES: FORMING A RELATIVELY THIN INSULATING LAYER OF OXIDE APPROXIMATELY 1 X 10**3 A THICK OVER A SEMICONDUCTOR SUBSTRATE OF SELECTED CONDUCTIVITY TYPE; FORMING A LAYER APPROXIMATELY 5 X 10**3A THICK OF POLYCRYSTALLINE SILICON OVER SAID INSULATING LAYER; FORMING A FIRST LAYER OF GLASS OVER SAID POLYCRYSTALLINE SILICON LAYER TO A THICKNESS APPROXIMATELY 10 X 10**3A THEREBY BEING SUBSTANTIALLY GREATER THAN THE THICKNESS OF THE INSULATING LAYER; MASKING AND ETCHING THROUGH SAID GLASS AND POLYSILICON LAYERS TO THE SURFACE OF SAID SILICON LAYER TO FORM AT LEAST TWO SPACED APART WINDOWS OF PREDETERMINED AREA FOR SOURCE AND DRAIN REGIONS, RESPECTIVELY; MASKING AN AREA GREATER THAN SAID PREDETERMINED AREA OVER SAID FIRST GLASS LAYER AT THE LOCATION OF AND SUBSTANTIALLY ALIGNED WITH AT LEAST ONE WINDOW OF SAID AT LEAST TWO WINDOWS CORRESPONDING TO SAID SOURCE REGION FOR INSURING PROPER ALIGNMENT OF A SUBSEQUENT DOUBLE DIFFUSION THEREAT AND THEN ETCHING THE GLASS AT SAID LARGER AREA AND THE INSULATING LAYER TO THE SURFACE OF SAID SUBSTRATE AT THE LOCATION OF SAID AT LEAST ONE WINDOW, SAID THICKNESS OF SAID FIRST GLASS LAYER THEREBY PREVENTING ANY ETCHING OF THE POLYSILICON LAYER THEREAT; DIFFUSING A FIRST CONDUCTIVITY TYPE IMPURITY DOPANT SELECTED FROM THE GROUP CONSISTING OF BORON, ALUMINUM, GALLIUM AND INDIUM THROUGH SAID AT LEAST ONE WINDOW INTO THE SURFACE OF SAID SUBSTRATE; REMOVING THE REMAINDER OF SAID FIRST GLASS LAYER AND ANY REMAINING INSULATING LAYER AT THE LOCATION OF THE OTHER WINDOW; SIMULTANEOUSLY DIFFUSING A SECOND CONDUCTIVITY TYPE IMPURITY DOPANT SELECTED FROM THE GROUP CONSISTING OF PHOSPHOROUS, ARSENIC, ANTIMONY AND BISMUTH THROUGH SAID AT LEAST TWO WINDOWS INTO THE SURFACE OF SAID SUBSTRATE TO PRODUCE A DOUBLE DIFFUSED SOURCE REGION AND A SINGLE DIFFUSED DRAIN REGION; THE INTERMEDIATE PORTION OF SAID INSULATING LAYER AND THE POLYCRYSTALLINE LAYER THEREBY PRODUCING A SILICON GATE WHILE THE POLYCRYSTALLINE LAYER EXTENDING BEYOND SAID AT LEAST TWO WINDOWS SERVES AS AN ELECTROSTATIC SHEILD; FORMING A SECOND LAYER OF GLASS OVER THE SURFACE OF THE POLYCRYSTALLINE SILICON AND THE SURFACE OF SAID SUBSTRATE EXPOSED BY SAID AT LEAST TWO WINDOWS; ETCHING CONTACT WINDOWS THROUGH SAID SECOND LAYER OF GLASS TO THE SURFACE OF SAID SUBSTRATE AT THE SOURCE AND DRAIN REGIONS AND THE SURFACE OF THE SILICON GATE; AND FORMING A LAYER OF METALLIZATION THERETHROUGH AND ETCHING A SELECTED PATTERN FOR FORMING DISCRETE METAL ELECTRODES.
Claim 2
Independent Claim
412 words
A METHOD OF MAKING A PLANAR METAL OXIDE SEMICONDUCTOR FIELD EFFECT DEVICE HAVING A RELATIVELY NARROW CHANNEL REGION AND A SILICON, GATE, WHEREIN THE IMPROVEMENT COMPRISES: FORMING A RELATIVELY THIN INSULATING LAYER OF OXIDE APPROXIMATELY 1 X 10**3 A THICK OVER A SEMICONDUCTOR SUBSTRATE OF SELECTED CONDUCTIVITY TYPE; FORMING A LAYER APPROXIMATELY 5 X 10**3A THICK OF POLYCRYSTALLINE SILICON OVER SAID INSULATING LAYER; FORMING A FIRST LAYER OF GLASS OVER SAID POLYCRYSTALLINE SILICON LAYER TO A THICKNESS APPROXIMATELY 10 X 10**3A THEREBY BEING SUBSTANTIALLY GREATER THAN THE THICKNESS OF THE INSULATING LAYER; MASKING AND ETCHING THROUGH SAID GLASS AND POLYSILICON LAYERS TO THE SURFACE OF SAID SILICON LAYER TO FORM AT LEAST TWO SPACED APART WINDOWS OF PREDETERMINED AREA FOR SOURCE AND DRAIN REGIONS, RESPECTIVELY; MASKING AN AREA GREATER THAN SAID PREDETERMINED AREA OVER SAID FIRST GLASS LAYER AT THE LOCATION OF AND SUBSTANTIALLY ALIGNED WITH AT LEAST ONE WINDOW OF SAID AT LEAST TWO WINDOWS CORRESPONDING TO SAID SOURCE REGION FOR INSURING PROPER ALIGNMENT OF A SUBSEQUENT DOUBLE DIFFUSION THEREAT AND THEN ETCHING THE GLASS AT SAID LARGER AREA AND THE INSULATING LAYER TO THE SURFACE OF SAID SUBSTRATE AT THE LOCATION OF SAID AT LEAST ONE WINDOW, SAID THICKNESS OF SAID FIRST GLASS LAYER THEREBY PREVENTING ANY ETCHING OF THE POLYSILICON LAYER THEREAT; DIFFUSING A FIRST CONDUCTIVITY TYPE IMPURITY DOPANT SELECTED FROM THE GROUP CONSISTING OF BORON, ALUMINUM, GALLIUM AND INDIUM THROUGH SAID AT LEAST ONE WINDOW INTO THE SURFACE OF SAID SUBSTRATE; REMOVING THE REMAINDER OF SAID FIRST GLASS LAYER AND ANY REMAINING INSULATING LAYER AT THE LOCATION OF THE OTHER WINDOW; SIMULTANEOUSLY DIFFUSING A SECOND CONDUCTIVITY TYPE IMPURITY DOPANT SELECTED FROM THE GROUP CONSISTING OF PHOSPHOROUS, ARSENIC, ANTIMONY AND BISMUTH THROUGH SAID AT LEAST TWO WINDOWS INTO THE SURFACE OF SAID SUBSTRATE TO PRODUCE A DOUBLE DIFFUSED SOURCE REGION AND A SINGLE DIFFUSED DRAIN REGION; THE INTERMEDIATE PORTION OF SAID INSULATING LAYER AND THE POLYCRYSTALLINE LAYER THEREBY PRODUCING A SILICON GATE WHILE THE POLYCRYSTALLINE LAYER EXTENDING BEYOND SAID AT LEAST TWO WINDOWS SERVES AS AN ELECTROSTATIC SHEILD; FORMING A SECOND LAYER OF GLASS OVER THE SURFACE OF THE POLYCRYSTALLINE SILICON AND THE SURFACE OF SAID SUBSTRATE EXPOSED BY SAID AT LEAST TWO WINDOWS; ETCHING CONTACT WINDOWS THROUGH SAID SECOND LAYER OF GLASS TO THE SURFACE OF SAID SUBSTRATE AT THE SOURCE AND DRAIN REGIONS AND THE SURFACE OF THE SILICON GATE; AND FORMING A LAYER OF METALLIZATION THERETHROUGH AND ETCHING A SELECTED PATTERN FOR FORMING DISCRETE METAL ELECTRODES.
Claim 3
Dependent Claim
15 words
The method as defined by claim 1 wherein the substrate is silicon having n-type conductivity.
Claim 4
Dependent Claim
16 words
The method as defined by claim 1 wherein said semiconductor substrate is silicon having p-type conductivity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-12 | 1978-11-11 | 1979-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-12 | 1982-11-11 | 1983-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-12 | 1986-11-11 | 1987-05-13 | $7700.00 | Window Closed / Lapsed |