US3882529A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Punch-through semiconductor diodes
Assignee: Texas Instruments Inc
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Filing: 1973-06-21
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Granted: 1975-05-06
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Expires: 1993-06-21
Abstract
Abstract A punch-through semiconductor device having three regions of alternate conductivity types which exhibit punch-through conduction characteristics similar to the breakdown characteristics of a Zener diode when a voltage equal to the punch-through voltage magnitude is applied across the device. The device is formed on a single semiconductor crystal for use in a number of different circuits requiring output characteristics similar to those of a Zener diode.
Inventors
- 👤 Jr Raymond M Warner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:55
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D99/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
309 words
In an integrated semiconductor circuit, a punch-through device for voltage regulation comprising: a semiconductor body of a first conductivity type having a planar surface, an elongated relatively highly doped first region of a second conductivity type disposed in said semiconductor body and extending to the planar surface of said semiconductor body, a plurality of relatively highly doped second regions of said second conductivity type disposed in said semiconductor body and extending to the planar surface thereof, said plurality of second regions being spaced from said elongated first region and disposed along the length thereof, terminal means ohmically connected to at least said elongated first region, said plurality of second regions being disposed in relatively closely spaced relationship with respect to said elongated first region with progressively increasing distance between each successive region and said elongated first region, to define a plurality of semiconductor junctions with said semiconductor body having depletion regions which respectively interact upon the application of progressively increasing voltages to said terminal means wherein each of said voltages is less than the avalanche voltage of the device, an elongated relatively highly doped third region of said second conductivity type disposed in said semiconductor body and extending to the planar surface thereof, said third region being located on the side of said plurality of second regions opposite from that of said elongated first region and being in spaced relationship with respect to said plurality of second regions, an insulating layer overlying the space between said elongated third region and said plurality of second regions, an elongated gate electrode on said insulating layer, a terminal ohmically connected to said gate electrode, and said device comprising a punch-through diode and said plurality of second regions cooperating with said elongated third region to define enhancement mode channels providing an enhancement mode metal oxide semiconductor device in series with said punch-through diode.
Claim 2
Dependent Claim
309 words
In an integrated semiconductor circuit, a punch-through device for voltage regulation comprising: a semiconductor body of a first conductivity type having a planar surface, an elongated relatively highly doped first region of a second conductivity type disposed in said semiconductor body and extending to the planar surface of said semiconductor body, a plurality of relatively highly doped second regions of said second conductivity type disposed in said semiconductor body and extending to the planar surface thereof, said plurality of second regions being spaced from said elongated first region and disposed along the length thereof, terminal means ohmically connected to at least said elongated first region, said plurality of second regions being disposed in relatively closely spaced relationship with respect to said elongated first region with progressively increasing distance between each successive region and said elongated first region, to define a plurality of semiconductor junctions with said semiconductor body having depletion regions which respectively interact upon the application of progressively increasing voltages to said terminal means wherein each of said voltages is less than the avalanche voltage of the device, an elongated relatively highly doped third region of said second conductivity type disposed in said semiconductor body and extending to the planar surface thereof, said third region being located on the side of said plurality of second regions opposite from that of said elongated first region and being in spaced relationship with respect to said plurality of second regions, an insulating layer overlying the space between said elongated third region and said plurality of second regions, an elongated gate electrode on said insulating layer, a terminal ohmically connected to said gate electrode, and said device comprising a punch-through diode and said plurality of second regions cooperating with said elongated third region to define enhancement mode channels providing an enhancement mode metal oxide semiconductor device in series with said punch-through diode.
Claim 3
Dependent Claim
262 words
In an integrated semiconductor circuit, a punch-through device for voltAge regulation comprising: a semiconductor body of a first conductivity type having a planar surface, a pair of relatively highly doped regions of a second conductivity type disposed in said semiconductor body in relatively closely spaced relationship with respect to each other and extending to the planar surface of said semiconductor body to define a pair of semiconductor junctions with said semiconductor body, terminal means ohmically connected to at least one of said pair of relatively highly doped regions of said second conductivity type, the space between said pair of relatively highly doped regions of said second conductivity type being predetermined in accordance with the relative doping of said regions to provide depletion regions associated with said semiconductor junctions which will interact upon the application of a voltage to said terminal means less than the avalanche voltage of the device, said pair of relatively highly doped regions including an inner region of substantially circular configuration to which said terminal means is ohmically connected and an outer region of substantially annular configuration disposed in concentric relationship with respect to each other, said outer region having a gap in a portion of its substantially annular configuration, said substantially annular configuration having a segment of enlarged width relative to its remaining portion, and the space between said inner and outer relatively highly doped regions being decreased in the area of the portion of said outer region of enlarged width as compared to the space between said inner region and the remaining portion of said outer region.
Claim 4
Dependent Claim
262 words
In an integrated semiconductor circuit, a punch-through device for voltAge regulation comprising: a semiconductor body of a first conductivity type having a planar surface, a pair of relatively highly doped regions of a second conductivity type disposed in said semiconductor body in relatively closely spaced relationship with respect to each other and extending to the planar surface of said semiconductor body to define a pair of semiconductor junctions with said semiconductor body, terminal means ohmically connected to at least one of said pair of relatively highly doped regions of said second conductivity type, the space between said pair of relatively highly doped regions of said second conductivity type being predetermined in accordance with the relative doping of said regions to provide depletion regions associated with said semiconductor junctions which will interact upon the application of a voltage to said terminal means less than the avalanche voltage of the device, said pair of relatively highly doped regions including an inner region of substantially circular configuration to which said terminal means is ohmically connected and an outer region of substantially annular configuration disposed in concentric relationship with respect to each other, said outer region having a gap in a portion of its substantially annular configuration, said substantially annular configuration having a segment of enlarged width relative to its remaining portion, and the space between said inner and outer relatively highly doped regions being decreased in the area of the portion of said outer region of enlarged width as compared to the space between said inner region and the remaining portion of said outer region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |