Insulated-gate field-effect transistor with punch-through effect element

Claim 2

An insulated-gate field-effect transistor formed in a semiconductor wafer of one conductivity type, comprising source and drain regions of a different conductivity type formed in said wafer, and at least one gate disposed on said wafer with an insulator layer interposed therebetween, characterized in that a separate region having said different conductivity type is provided in said wafer, said separate region forming a P-n junction with said wafer in the vicinity of said source region, said separate region being connected with one of said at least one gate by means of a lead wire, whereby current flows between said one gate and said source region through said separate region due to punch-through at a voltage lower than the breakdown voltage of said insulator layer.

Claim 3

A transistor according to claim 1, in which said semiconductor wafer is of p-type silicon and said different conductivity type is n-type.

Claim 4

A transistor according to claim 1, in which said semiconductor wafer is of n-type silicon and said different conductivity type is p-type.

Claim 5

A transistor according to claim 1, in which said transistor further comprises an island region of said different conductivity type formed in said wafer between said source and drain regions.

Claim 6

An MOS type device in an integrated array of MOS type devices with means to avoid destructive breakdown comprising: a body of semiconductive material including a substrate of a first conductivity type; a layer of insulating material covering at least a portion of a surface of said body, said layer of insulating material exhibiting destructive breakdown at a first voltage level; a layer of conductive material disposed on said layer of insulating material over said surface portion to serve as an electrode; an initial region of semiconductive material of a second conductivity type in said surface spaced from said portion; a conductive interconnection between said electrode and said initial region; said region being spaced from another region of said second conductivity type by a distance through material of said substrate of said first conductivity type to defIne a channel region exhibiting punch-through at a voltage level less than said voltage level, said channel region not being operated as part of an active MOS type device.

Claim 7

An MOS type device in an integrated array of MOS type devices with means to avoid destructive breakdown comprising: a body of semiconductive material including a substrate of a first conductivity type; a layer of insulating material covering at least a portion of a surface of said body, said layer of insulating material exhibiting destructive breakdown at a first voltage level; a layer of conductive material disposed on said layer of insulating material over said surface portion to serve as an electrode; an initial region of semiconductive material of a second conductivity type in said surface spaced from said portion; a conductive interconnection between said electrode and said initial region; said region being spaced from another region of said second conductivity type by a distance through material of said substrate of said first conductivity type to defIne a channel region exhibiting punch-through at a voltage level less than said voltage level, said channel region not being operated as part of an active MOS type device.

Claim 8

The subject matter of claim 5 wherein: said portion of a surface of said body is a channel region of an MOS type transistor.

Claim 9

An MOS type transistor in an integrated array of MOS type transistors with means to avoid destructive breakdown comprising: a first region of semiconductive material of a first type conductivity; second and third regions of semiconductive material of a second type of conductivity in a surface of said first region to serve as source and drain regions, said second and third regions being spaced a distance to define a channel region therebetween; a layer of insulating material covering at least said channel region, said layer of insulating material exhibiting destructive breakdown at a first voltage level; a layer of conductive material disposed on said layer of insulating material over said channel region to serve as a gate electrode; a fourth region of semiconductive material of said second type in said surface; a conductive interconnection between said gate electrode and said fourth region; said fourth region being spaced from another region of the same type by a distance to define an additional channel region exhibiting punch-through at a voltage level less than said first voltage level and a voltage level less than that at which avalanche breakdown of the diode formed by said fourth and first regions occurs, said additional channel region not being operated as part of an active MOS type device.

Claim 10

An MOS type transistor in an integrated array of MOS type transistors with means to avoid destructive breakdown comprising: a first region of semiconductive material of a first type conductivity; second and third regions of semiconductive material of a second type of conductivity in a surface of said first region to serve as source and drain regions, said second and third regions being spaced a distance to define a channel region therebetween; a layer of insulating material covering at least said channel region, said layer of insulating material exhibiting destructive breakdown at a first voltage level; a layer of conductive material disposed on said layer of insulating material over said channel region to serve as a gate electrode; a fourth region of semiconductive material of said second type in said surface; a conductive interconnection between said gate electrode and said fourth region; said fourth region being spaced from another region of the same type by a distance to define an additional channel region exhibiting punch-through at a voltage level less than said first voltage level and a voltage level less than that at which avalanche breakdown of the diode formed by said fourth and first regions occurs, said additional channel region not being operated as part of an active MOS type device.

Claim 11

The subject matter of claim 5 wherein: said portion of a surface of said body is semiconductor region of an MOS-type capacitor.

Claim 12

The subject matter of claim 7 wherein: said another region is one of said second and third regions that has a direct interconnection to said first region.

Claim 13

The subject matter of claim 7 wherein: said another region is a fifth region that has a direct interconnection with said first region and said fourth and fifth regions are both spaced from said second and third regions by a distance greater than the spacing between said fourth and fifth regions.

Claim 14

The subject matter of claim 7 wherein: said channel region between said second and third regions is free of an inversion layer in the absence of a voltage on said gate electrodes.

Claim 15

The subject matter of claim 7 wherein: said second, third, fourth and said another region are all of the same resistivity, impurity concentration gradient and thickness.