Complementary field effect transistor memory cell

Claim 2

A memory circuit having a selected state and a quiescent state, comprising: a four transistor storage cell, each transistor having a first and second current conducting electrode, a control electrode and a substrate electrode, said storage cell comprising first and second branch circuits, each branch circuit including a first conductivity type transistor and a second type conductivity type transistor having their first current conducting terminals connected to a common point, said common point in each branch circuit also being connected to the control electrodes of the transistors in the other branch circuit, and common control signal bias means connected between the second current conducting terminal of said first conductivity type transistor in each branch circuit and its substrate terminal, said bias means providing a first bias condition for sustaining said first conductivity type transistors in enhancement mode during said quiescent state causing substantially zero current to flow in said branch circuits and providing a second bias condition causing at least one of said first conductivity type transistors to operate in a depletion mode during said selected state causing substantial current to flow in one of said branch circuits.

Claim 3

The memory circuit of claim 1 further including means for applying a reference potential to the second current conducting electrode of said second conductivity type transistor in each of said branch circuits at least during said quiescent state.

Claim 4

The memory circuit of claim 2 further including means connected to the second current conducting terminal of said second conductivity type transistors of at least one of said branch circuits for determining the presence of current flowing in said branch circuit during said selected state.

Claim 5

The memory circuit of claim 3 further including means for selectively applying a driving potential to one of said second current conducting terminals of said second conductivity type transistors during said selected state to provide a change in the logical state of said storage cell.

Claim 6

The memory circuit of claim 1 where said control signal bias means comprises a fixed bias potential connected to the substrate terminals of said first conductivity type transistors and a variable bias potential connected to said second current conducting terminals of said first conductivity type transistors, said second variable bias potential having different potential levels corresponding to said selected and quiescent states.

Claim 7

The memory circuit of claim 1, wherein said first conductivity type transistors are N-type field effect transistors and said second conductivity type transistors are P-type field effect transistors.

Claim 8

The memory circuit of claim 2 further including substantially equal load impedance means connected to the second current conducting terminal of each second conducting type transistors.

Claim 9

The memory circuit of claim 7 wherein at least one of said load impedance means includes a sense amplifier circuit.

Claim 10

a memory system comprising: a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a plurality of memory cells, each memory cell comprising; four field effect transistors connected in a first and second branch circuit, each branch circuit including a P-type transistor having its drain connected to the drain of a N-type transistor, the drains of the transistors in each branch circuit being connected to the gates of the transistors in the other branch circuit, the source of each N-type transistor being connected to one of said word lines, the source of one of said P-type transistors being connected to one of said first bit lines and the source of the other said P-type transistors being connected to one of said second bit lines; means for establishing a potential beTween said word lines and said first and second bit lines for sustaining binary logical states in said memory cells in a stable quiescent state; signal control means associated with said N-type transistors for selectively causing at least one of said N-type transistors to operate in a depletion mode to provide current flow in one of said branch circuits between a selected word line and at least one of said bit lines during an selected state; and means for determining the presence of current flow in said second bit lines for providing an indication of the logical state of each of said memory cells during said selected state.

Claim 11

a memory system comprising: a plurality of word lines; a plurality of first bit lines; a plurality of second bit lines; a plurality of memory cells, each memory cell comprising; four field effect transistors connected in a first and second branch circuit, each branch circuit including a P-type transistor having its drain connected to the drain of a N-type transistor, the drains of the transistors in each branch circuit being connected to the gates of the transistors in the other branch circuit, the source of each N-type transistor being connected to one of said word lines, the source of one of said P-type transistors being connected to one of said first bit lines and the source of the other said P-type transistors being connected to one of said second bit lines; means for establishing a potential beTween said word lines and said first and second bit lines for sustaining binary logical states in said memory cells in a stable quiescent state; signal control means associated with said N-type transistors for selectively causing at least one of said N-type transistors to operate in a depletion mode to provide current flow in one of said branch circuits between a selected word line and at least one of said bit lines during an selected state; and means for determining the presence of current flow in said second bit lines for providing an indication of the logical state of each of said memory cells during said selected state.

Claim 12

The memory system of claim 9 wherein said signal control means comprises a source of fixed negative substrate bias potential connected to the substrates of N-type transistors and means for varying the potential applied to said word lines to cause said N-type transistors to operate in enhancement mode during said quiescent state and in depletion mode during said selected state.

Claim 13

The memory system of claim 9 further including variable drive potential means connected to said bit lines for selectively changing the logical state of said memory cells during said selected state.

Claim 14

The memory system of claim 10 wherein said means for varying the potential applied to said word lines includes means to provide a reverse substrate-to-source bias during said quiescent state and substantially zero substrate-to-source bias during at least a portion of the time said cell is in said selected state.