Patent US2994642A successfully refreshed from Google Patents.
Patent US3882460A successfully refreshed from Google Patents.
US3882460A
Expired / Lapsed
US
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Serial transfer error detection logic
Assignee: Unisys Corp
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Filing: 1973-11-02
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Granted: 1975-05-06
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Expires: 1993-11-02
Abstract
Abstract In a serial transfer channel, a single failing component may cause an even multiple of bit errors to occur in a message. By generating a parity bit for the overall parity of the contents of the transfer register, during information transfer, and using this overall parity bit to check the overall parity of the receive register, all error occurrences resulting from the failing component, including even multiple errors, are detected. Another embodiment detects all errors introduced during transfer of information to or from the transmission line by generating, at the receiving end and/or at the sending end, an intermediate parity bit for all information bits transferred from the transmission line to the receiving register and/or from the sending register to the transmission line.
Inventors
- 👤 Jr Walter Scott Bennett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
124 words
Error detection logic for a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end and a serial input, parallel output receive register at the othEr end, comprising: means for generating an overall parity bit in response to all the bits in said transfer register during each transfer cycle; means for checking parity of all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the overall parity bits received from said overall parity bit generating means; and means for transferring the overall parity bits from said parity bit generating means to said parity checking means separately from the bits in said transfer register.
Claim 2
Dependent Claim
124 words
Error detection logic for a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end and a serial input, parallel output receive register at the othEr end, comprising: means for generating an overall parity bit in response to all the bits in said transfer register during each transfer cycle; means for checking parity of all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the overall parity bits received from said overall parity bit generating means; and means for transferring the overall parity bits from said parity bit generating means to said parity checking means separately from the bits in said transfer register.
Claim 3
Dependent Claim
41 words
The error detection logic of claim 1 wherein said parity bits transferring means, comprises: a separate transmission path in said serial transfer channel for transmitting said overall parity bits from said overall parity bit generating means to said parity checking means.
Claim 4
Dependent Claim
28 words
The error detection logic of claim 2 wherein said means for generating an overall parity bit, and said means for checking parity are multiple input Exclusive OR gates.
Claim 5
Dependent Claim
176 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: means for generating a plurality of overall parity bits, each of said parity bits being determined by the character of a particular one or more of said information bits which particular bits are in turn determined by the order of serial transmission of the information bits constituting said message; means for checking parity of said message at a receiving location, said parity checking means performing a plurality of parity checks for each received message, each parity check being responsive to a particular one of the overall parity bits and to a particular one or more of the received information bits constituting said message as determined by the order of serial reception thereof; and means for transferring the overall parity bits from said parity bit generating means to said parity checking means separately from the bits in said communication path.
Claim 6
Dependent Claim
176 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: means for generating a plurality of overall parity bits, each of said parity bits being determined by the character of a particular one or more of said information bits which particular bits are in turn determined by the order of serial transmission of the information bits constituting said message; means for checking parity of said message at a receiving location, said parity checking means performing a plurality of parity checks for each received message, each parity check being responsive to a particular one of the overall parity bits and to a particular one or more of the received information bits constituting said message as determined by the order of serial reception thereof; and means for transferring the overall parity bits from said parity bit generating means to said parity checking means separately from the bits in said communication path.
Claim 7
Dependent Claim
23 words
The error detection logic of claim 4 wherein said overall parity bits transferring means comprises: a transmission path separate from said communication path.
Claim 8
Dependent Claim
27 words
The error detection logic of claim 5 wherein said means for generating overall parity bits, and said means for checking parity are multiple input Exclusive OR gates.
Claim 9
Independent Claim
120 words
A method for detecting error occurrences in a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end and a serial input, parallel output receive register at the other end, comprising: generating an overall parity bit at said one end in response to all the bits in said transfer register during each transfer cycle; transferring the overall parity bits generated to said other end of the single transmission path separately from the bits in said transfer register; and parity checking at said other end all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the overall parity bits received.
Claim 10
Independent Claim
120 words
A method for detecting error occurrences in a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end and a serial input, parallel output receive register at the other end, comprising: generating an overall parity bit at said one end in response to all the bits in said transfer register during each transfer cycle; transferring the overall parity bits generated to said other end of the single transmission path separately from the bits in said transfer register; and parity checking at said other end all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the overall parity bits received.
Claim 11
Independent Claim
163 words
A method for detecting error occurrences in a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: generating overall parity bits at said one location, said parity bits being determined by the character of a particular one or more of said information bits which particular bits are in turn determined by the order of serial transmission of the information bits constituting said message; transferring the overall parity bits generated to said another location separately from said information bits; and checking parity of said message at said another location, said parity checking performing a plurality of parity checks for each receivEd message, each parity check being responsive to a particular one of the received overall parity bits and to a particular one or more of the received information bits constituting said message as determined by the order of serial reception thereof.
Claim 12
Independent Claim
163 words
A method for detecting error occurrences in a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: generating overall parity bits at said one location, said parity bits being determined by the character of a particular one or more of said information bits which particular bits are in turn determined by the order of serial transmission of the information bits constituting said message; transferring the overall parity bits generated to said another location separately from said information bits; and checking parity of said message at said another location, said parity checking performing a plurality of parity checks for each receivEd message, each parity check being responsive to a particular one of the received overall parity bits and to a particular one or more of the received information bits constituting said message as determined by the order of serial reception thereof.
Claim 13
Dependent Claim
99 words
Error detection logic for a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end thereof and a serial input, parallel output receive register at the other end thereof, comprising: means for generating an intermediate parity bit during each transfer cycle for each bit transferred on said serial transfer channel; and means for checking parity of all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the intermediate parity bit received from said intermediate parity bit generating means.
Claim 14
Dependent Claim
99 words
Error detection logic for a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end thereof and a serial input, parallel output receive register at the other end thereof, comprising: means for generating an intermediate parity bit during each transfer cycle for each bit transferred on said serial transfer channel; and means for checking parity of all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the intermediate parity bit received from said intermediate parity bit generating means.
Claim 15
Dependent Claim
26 words
The error detection logic of claim 9 wherein said intermediate parity bit generating means is situated at the receive register end of said serial transfer channel.
Claim 16
Dependent Claim
63 words
The error detection logic of claim 10 wherein said means for generating an intermediate parity bit; comprises: a two input Exclusive OR gate having one of its inputs connected to the output of said transfer register; and a D-type flip-flop having its input driven by the output of said OR gate and its output connected to the other input of said OR gate.
Claim 17
Dependent Claim
63 words
The error detection logic of claim 9 wherein said means for generating an intermediate parity bit, comprises: a two input Exclusive OR gate having one of its inputs connected to the output of said transfer register; and a D-type flip-flop having its input driven by the output of said OR gate and its output connected to the other input of said OR gate.
Claim 18
Dependent Claim
129 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: a binary storage means; means for generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each information bit transferred on said serial transfer channel and the output from said binary storage means, each newly generated intermediate parity bit being loaded into said storage means to be read out at the next information bit transfer; and means for checking parity of said message at said another location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits.
Claim 19
Dependent Claim
129 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: a binary storage means; means for generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each information bit transferred on said serial transfer channel and the output from said binary storage means, each newly generated intermediate parity bit being loaded into said storage means to be read out at the next information bit transfer; and means for checking parity of said message at said another location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits.
Claim 20
Dependent Claim
29 words
The error detection logic of claim 13 wherein said intermediate parity bit generating means and said storage means is situated at said another location of said serial transfer channel.
Claim 21
Dependent Claim
61 words
The error detection logic of claim 14 wherein said means for generating an intermediate parity bit, comprises: a two input Exclusive OR gate having one of its inputs connected to said serial transfer channel; and a D-type flip-flop having its input driven by the output of said OR gate and its output connected to the other input of said OR gate.
Claim 22
Dependent Claim
61 words
The error detection logic of claim 13 wherein said means for generating an intermediate parity bit, comprises: a two input Exclusive OR gate having one of its inputs connected to said serial transfer channel; and a D-type flip-flop having its input driven by the output of said OR gate and its output connected to the other input of said OR gate.
Claim 23
Independent Claim
108 words
A method for detecting error occurrences in a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end and a serial input, parallel output receive register at the other end, comprising: generating an intermediate parity bit during each transfer cycle, said intermediate parity bit being determined by the character of the bit transferrEd on said serial transfer channel and the character of the immediately previous intermediate parity bit; and checking parity of all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the generated intermediate parity bits.
Claim 24
Independent Claim
108 words
A method for detecting error occurrences in a serial transfer channel having a single transmission path and utilizing a parallel input, serial output transfer register at one end and a serial input, parallel output receive register at the other end, comprising: generating an intermediate parity bit during each transfer cycle, said intermediate parity bit being determined by the character of the bit transferrEd on said serial transfer channel and the character of the immediately previous intermediate parity bit; and checking parity of all the bits in said receive register during each transfer cycle in response to the bits in said receive register and the generated intermediate parity bits.
Claim 25
Independent Claim
102 words
A method for detecting error occurrences in a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each bit transferred on said serial transfer channel and the character of the immediately previous intermediate parity bit; and checking parity of said message at a receiving location, said parity checking being responsive to the information bits in said message and to the intermediate parity bits.
Claim 26
Independent Claim
102 words
A method for detecting error occurrences in a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each bit transferred on said serial transfer channel and the character of the immediately previous intermediate parity bit; and checking parity of said message at a receiving location, said parity checking being responsive to the information bits in said message and to the intermediate parity bits.
Claim 27
Dependent Claim
129 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: a binary storage means; means for generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each information bit transferred on said serial transfer channel and the output from said binary storage means, each newly generated intermediate parity bit being loaded into said storage means to be read out at the next information bit transfer; and means for checking parity of said message at said one location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits.
Claim 28
Dependent Claim
129 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: a binary storage means; means for generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each information bit transferred on said serial transfer channel and the output from said binary storage means, each newly generated intermediate parity bit being loaded into said storage means to be read out at the next information bit transfer; and means for checking parity of said message at said one location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits.
Claim 29
Dependent Claim
159 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: a binary storage means; means for generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each information bit transferred on said serial transfer channel and the output from said binary storage means, each newly generated intermediate parity bit being loaded into said storage means to be read out at the next information bit transfer; means for checking parity of said message at said one location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits; and means for checking parity of said message at said another location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits.
Claim 30
Dependent Claim
159 words
Error detection logic for a serial transfer channel wherein a message consisting of a plurality of binary information bits is transferred from one location to another over the same communication path one bit at a time, comprising: a binary storage means; means for generating intermediate parity bits, each of said intermediate parity bits being determined by the character of each information bit transferred on said serial transfer channel and the output from said binary storage means, each newly generated intermediate parity bit being loaded into said storage means to be read out at the next information bit transfer; means for checking parity of said message at said one location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits; and means for checking parity of said message at said another location, said parity checking means being responsive to the information bits in said message and to the intermediate parity bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |