US3882459A
Expired / Lapsed
US
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Deadtracking system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1974-05-02
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Granted: 1975-05-06
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Expires: 1994-05-02
Abstract
Abstract A microprogrammed peripheral controller includes a deskew buffer including a plurality of clocked storage devices. Pairs of the clock storage devices of each register provides storage for a single information channel. Each channel is driven from a separate clock circuit which is enabled for operation only when circuits associated with the channel detect that information signals are being received by the channel indicating that the channel is ''''active'''' at the start of an actual record. The circuits for detecting the activity of a channel are included within the circuits which detect conditions occurring during the reading operation indicative of a channel failure. When the circuits detect that the channel is not active, they operate to switch a storage device to a predetermined state indicating a channel failure which causes the channel to be ''''dead tracked''''. Thereafter, both storage devices of a predetermined one of the pairs of the channel are switched to the same predetermined state for the remainder of the record reading operation causing correction circuits included in the controller to correct signal channel error conditions within that channel in the same manner that the circuits correct for other types of error conditions.
Inventors
- 👤 George J Barlow
- 👤 Donald R Taylor
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:21
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/20
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
387 words
Apparatus for detecting inactivity in a plurality of tracks of a medium read by a device and applied to a corresponding number of channels of a data recovery system, each of said channels including a number of series coupled deskew buffer registers including first and second bistable storage means and clocking means, said first and second bistable storage means of at least a first one of said buffer registers of each channel being coupled to said clocking means for receiving of clocking signals defining bit intervals for sampling information signals read from said tracks during said intervals and each byte of information corresponding to a group of bit signals simultaneously recorded on said tracks of said medium and then applied by said device as signal transistions to said channels, said apparatus comprising: a plurality of input transition detector means, the input detector means of each channel being operative in response to said signal transitions to produce pulses representative of a binary ONE and a binary ZERO to first and second lines respectively coupled to said first and second bistable storage means of said first one of said buffer registers; a plurality of activity circuit means corresponding in number to said input detector means, each coupled to said first and second lines of a different one of said plurality of said input detector means and being operative to switch from a first to a second state in response to pulses applied to said first and second lines; a corresponding number of bistable channel failure indicator means, each coupled to a different one of said activity circuit means and to a corresponding one of said clocking means of said channel; and, control means being operative upon detecting that an initial group of bytes have been received from said device to generate signals for enabling each of said clocking means for generating said sets of clocking signals, said control means being coupled to each of said channel failure indicator means and operative to condition said each channel failure means concurrent with generating said signals to be switched from a first to a second state only when said activity circuit means is in said first state for inhibiting the enabling of said channel clocking means by said signals to prevent transfer of incorrect information through each channel of an inactive track.
Claim 2
Dependent Claim
387 words
Apparatus for detecting inactivity in a plurality of tracks of a medium read by a device and applied to a corresponding number of channels of a data recovery system, each of said channels including a number of series coupled deskew buffer registers including first and second bistable storage means and clocking means, said first and second bistable storage means of at least a first one of said buffer registers of each channel being coupled to said clocking means for receiving of clocking signals defining bit intervals for sampling information signals read from said tracks during said intervals and each byte of information corresponding to a group of bit signals simultaneously recorded on said tracks of said medium and then applied by said device as signal transistions to said channels, said apparatus comprising: a plurality of input transition detector means, the input detector means of each channel being operative in response to said signal transitions to produce pulses representative of a binary ONE and a binary ZERO to first and second lines respectively coupled to said first and second bistable storage means of said first one of said buffer registers; a plurality of activity circuit means corresponding in number to said input detector means, each coupled to said first and second lines of a different one of said plurality of said input detector means and being operative to switch from a first to a second state in response to pulses applied to said first and second lines; a corresponding number of bistable channel failure indicator means, each coupled to a different one of said activity circuit means and to a corresponding one of said clocking means of said channel; and, control means being operative upon detecting that an initial group of bytes have been received from said device to generate signals for enabling each of said clocking means for generating said sets of clocking signals, said control means being coupled to each of said channel failure indicator means and operative to condition said each channel failure means concurrent with generating said signals to be switched from a first to a second state only when said activity circuit means is in said first state for inhibiting the enabling of said channel clocking means by said signals to prevent transfer of incorrect information through each channel of an inactive track.
Claim 3
Dependent Claim
79 words
The apparatus of claim 1 further including: means coupled to said channel failure indicator means of said each channel and to said first and second bistable storage means of a predetermined one of said deskew buffer registers, said means being conditioned by said channel indicator means when in said second state to force said first and second bistable means to the same predetermined state during succeeding bit intervals signaling that the information transferred through said each channel requires correction.
Claim 4
Dependent Claim
58 words
The apparatus of claim 2 further including checking means coupled to receive byte signals from a last one of said buffer registers, said checking means being operative in accordance with the results of performing a checking operation upon said by signals to generate a signal for correcting information stored in said first bistable means of each said channel.
Claim 5
Dependent Claim
143 words
The apparatus of claim 1 further including: a plurality of enabling switching circuit means, each coupled to a different one of said clocking means and to a corresponding one of said channel failure indicator means, each said enabling circuit means being selectively enabled in response to pulses from one of said lines during a predetermined interval defined by said signals generated by said control means only when said channel failure indicator means switches from said first to second state during said predetermined interval and each of said channel failure means including input gating means coupled to receive status indicative of a channel failure detected during the processing of subsequently received data bytes, said each channel failure means being conditioned by said control means to switch from said first to said second state following said predetermined interval only in response to said status signals.
Claim 6
Dependent Claim
102 words
The apparatus of claim 4 wherein said apparatus further includes: a plurality of decoder circuit means, each coupled to different selected ones of said activity circuit means and each operative to generate output signals indicating that pulses are being received from said device at a predetermined rate and circuit means coupled to said plurality of decoder circuit means, said circuit means being operative to condition said control means to generate said signals only upon being conditioned by continuous application of said output signals for a predetermined period indicating that processing of a number of a predetermined type of bytes has been completed.
Claim 7
Dependent Claim
75 words
The apparatus of claim 5 wherein said bytes received from said device comprise a data record having preamble and postamble sets of bytes bracketing data bytes and separated by a byte having a predetermined code of said record for enabling the synchronization of each of said clocking means to said data recovery apparatus, said control means including means operative to generate said signals only during receipt of bytes of said preamble for said predetermined period.
Claim 8
Dependent Claim
50 words
The apparatus of claim 6 wherein said control means includes means operative in response to a signal indicating the sensing of said byte having said predetermined code to inhibit each of said channel failure indicator means from being switched to said second state by said activity circuit means associated therewith.
Claim 9
Dependent Claim
79 words
The apparatus of claim 7 wherein each of said activity circuit means includes bistable storage means including first and second gating means coupled to receive pulses from said first and second lines and hold gating means coupled to said control means, said control means including timing means for generating signals at predetermined intervals for enabling the resetting of said bistable means in the absence of pulses being received from said first and second lines indicative of an inactive track.
Claim 10
Dependent Claim
91 words
The apparatus of claim 8 wherein each of said input transition detector circuits includes; a pair of series connected clocked bistable means, a first one of said pair being connected to receive said transistion signals from said device and each of said bistable means being operative to generate pairs of complementary output signals and first and second AND gating means connected to receive a different predetermined one of said pairs of output signals to produce pulses on said first and second lines respectively in response to positive and negative signal transitions.
Claim 11
Dependent Claim
272 words
A controller system including data recovery apparatus for reliably processing information bytes of data records recorded within a plurality of tracks on a magnetic medium, each of said data records including at least a preamble portion having a plurality of bytes for synchronizing the timing of said system to the information bytes being read, each byte of information corresponding to a group of bit signals simultaneously recorded on said tracks and applied to said system as bilevel signals, said data recovery apparatus including a plurality of channels corresponding in number to said tracks, each channel comprising: a plurality of series coupled bistable buffer means, a first one of said buffer means coupled to receive pulses representative of binary ONE and binary ZERO information derived from said bilevel signals; clocking means coupled to at least said first one of said buffer means, said clocking means operative to apply clocking signals defining bit intervals for sampling pulses derived from a corresponding one of said tracks; and, channel failure indicator means coupled to said clocking means and to receive said pulses, said indicator means including means operative in response to a control signal indicating a start of a predetermined interval during which only bytes of said preamble portion are received to switch said channel failure indicator means from a first to a second state in the absence of receiving said pulses within a predetermined interval indicating the presence of an inactive track condition, said channel failure indicator means when in said second state being operative to inhibit the enabling of said clocking means for generating said clocking signals during the processing of said data record.
Claim 12
Dependent Claim
272 words
A controller system including data recovery apparatus for reliably processing information bytes of data records recorded within a plurality of tracks on a magnetic medium, each of said data records including at least a preamble portion having a plurality of bytes for synchronizing the timing of said system to the information bytes being read, each byte of information corresponding to a group of bit signals simultaneously recorded on said tracks and applied to said system as bilevel signals, said data recovery apparatus including a plurality of channels corresponding in number to said tracks, each channel comprising: a plurality of series coupled bistable buffer means, a first one of said buffer means coupled to receive pulses representative of binary ONE and binary ZERO information derived from said bilevel signals; clocking means coupled to at least said first one of said buffer means, said clocking means operative to apply clocking signals defining bit intervals for sampling pulses derived from a corresponding one of said tracks; and, channel failure indicator means coupled to said clocking means and to receive said pulses, said indicator means including means operative in response to a control signal indicating a start of a predetermined interval during which only bytes of said preamble portion are received to switch said channel failure indicator means from a first to a second state in the absence of receiving said pulses within a predetermined interval indicating the presence of an inactive track condition, said channel failure indicator means when in said second state being operative to inhibit the enabling of said clocking means for generating said clocking signals during the processing of said data record.
Claim 13
Dependent Claim
102 words
The control system of claim 10 wherein said data recovery apparatus further includes: control means including; first means being conditioned by said system to switch from a first to a second state generating a first control signal when a predetermined number of bytes of said preamble portion has been read from said plurality of tracks and second means coupled to said first means and to each of said channel failure indicator means, said second means in response to said first control signal being operative to generate signal during successive intervals for conditioning said absence of said pulses within said predetermined time interval.
Claim 14
Dependent Claim
94 words
The system of claim 11 wherein said systeM being operative to condition said first means upon detecting receipt of all of the bytes of said preamble portion signaling the end of said predetermined interval to switch state inhibiting generation of said first control signal and said second means being operative in the absence of said first control signal to inhibit generation of said signals for the remainder of said record disabling each of said channel failure indicator means from switching state in response to an inactive track condition causing disabling of said clocking means.
Claim 15
Dependent Claim
74 words
The system of claim 12 wherein said each channel further includes activity circuit means coupled to receive said pulses representative of binary ONE and binary ZERO information and coupled to said second means and to said channel failure indicator means, said second means being operative to condition said activity circuit means during said predetermined intervals to generate signals indicating said absence of said pulses for causing the switching of said channel failure indicator means.
Claim 16
Dependent Claim
104 words
The system of claim 13 wherein said each channel further includes transition detector means coupled to receive said bilevel signals derived from a track associated therewith, said detector means including; a pair of series connected clocked bistable means, a first one of said pair being connected to receive said bilevel signals and each of said bistable means being operative to generate pairs of complementary output signals and first and second AND gating means connected to receive a different predetermined one of said pairs of output signals and operative to produce said pulses in response to positive and negative going transitions in said bilevel signals.
Claim 17
Dependent Claim
90 words
The system of claim 10 wherein said plurality of series coupled bistable buffer means of each channel each include first and second bistable storage means and wherein said channel further includes means coupled to said channel failure indicator means and to a predetermined one of said buffer means, said means being conditioned by said channel failure indicator means when in said second state to force said first and second bistable means to the same predetermined state during succeeding bit intervals signaling that the signals transferred through said channel requires correction.
Claim 18
Dependent Claim
80 words
The system of claim 15 wherein data recovery apparatus further includes checking means coupled to receive byte signals from a last one of said buffer means of each of said channel, said checking means being operative in accordance with the results of performing a checking operation upon said byte signals to generate a signal for correcting said signals stored in said first bistable means of said last one of said buffer means during the subsequent processing of said data record.
Claim 19
Dependent Claim
124 words
The system of claim 11 wherein said each channel further includes: enabling switching circuit means coupled to said channel clocking means, said channel failure indicator means and to said first means, said enabling circuit means being selectively enabled in response to pulses representative of binary ONE information during said first control signal only when said channel failure indicator means switches from said first to said second state and said channel failure means including input gating means coupled to receive status signals indicative of a potential channel failure detected during the processing bytes of said data record, said channel failure means being conditioned to switch from said first to said second state in response to said status signals at the completion of said predetermined interval.
Claim 20
Dependent Claim
320 words
In a data recovery system, apparatus for detecting at least first and second types of potential failure conditions during a transfer of information pulses through one of a plurality of channels, each of said channels including input means for generating pulses representative of a bit of information to first and second output lines, each byte of information corresponding to a Group of bit signals simultaneously recorded on a medium being read and said each channel further including a plurality of buffer registers, each of said registers including first and second bistable storage means and clocking means coupled to a first one of said buffer registers for applying sets of clocking signals defining bit intervals for sampling said pulses during said intervals, said apparatus comprising: a plurality of activity circuit means, each coupled to said first and second output lines of a channel, said each activity circuit means being operative to switch from a first to a second state in response to said pulses; a plurality of bistable channel failure indicator means, each coupled to a different one of said activity circuit means and to a corresponding one of said clocking means, each of said channel indicator means including at least first and second means for receiving signals representative of first and second types of potential failure conditions, said first means being coupled to said activity circuit means and operative only during an initial transfer of pulses to said input means representative of a predetermined type of byte signals for synchronizing the operation of said clocking means to cause said channel failure means to switch from a first to a second state when said activity circuit is in said first state and said second means being operative to cause said channel failure means to switch from said first to said second state only after the disabling of said first means at the end of receiving said predetermined type of byte signals.
Claim 21
Dependent Claim
320 words
In a data recovery system, apparatus for detecting at least first and second types of potential failure conditions during a transfer of information pulses through one of a plurality of channels, each of said channels including input means for generating pulses representative of a bit of information to first and second output lines, each byte of information corresponding to a Group of bit signals simultaneously recorded on a medium being read and said each channel further including a plurality of buffer registers, each of said registers including first and second bistable storage means and clocking means coupled to a first one of said buffer registers for applying sets of clocking signals defining bit intervals for sampling said pulses during said intervals, said apparatus comprising: a plurality of activity circuit means, each coupled to said first and second output lines of a channel, said each activity circuit means being operative to switch from a first to a second state in response to said pulses; a plurality of bistable channel failure indicator means, each coupled to a different one of said activity circuit means and to a corresponding one of said clocking means, each of said channel indicator means including at least first and second means for receiving signals representative of first and second types of potential failure conditions, said first means being coupled to said activity circuit means and operative only during an initial transfer of pulses to said input means representative of a predetermined type of byte signals for synchronizing the operation of said clocking means to cause said channel failure means to switch from a first to a second state when said activity circuit is in said first state and said second means being operative to cause said channel failure means to switch from said first to said second state only after the disabling of said first means at the end of receiving said predetermined type of byte signals.
Claim 22
Dependent Claim
78 words
The apparatus of claim 18 further including: means coupled to said channel failure indicator means of said each channel and to said first and second bistable storage means of a predetermined one of said buffer registers, said means being conditioned by said channel indicator means when in said second state to force said first and second bistable means to the same predetermined state during succeeding bit intervals signaling that the information transferred through said each channel requires correction.
Claim 23
Dependent Claim
58 words
The apparatus of claim 19 further including checking means coupled to receive byte signals from a last one of said buffer registers, said checking means being operative in accordance with the results of performing a checking operation upon said byte signals to generate a signal for correcting information stored in said first bistable means of each said channel.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |