Patent US2937551A successfully refreshed from Google Patents.
Patent US3882455A successfully refreshed from Google Patents.
US3882455A
Expired / Lapsed
US
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Configuration control circuit for control and maintenance complex of digital communications system
Assignee: AG Communication Systems Corp
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Filing: 1973-09-14
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Granted: 1975-05-06
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Expires: 1993-09-14
Abstract
Abstract A digital communications system includes duplicate copies of a central processor, instruction storage, process storage and peripheral controllers, together with duplicate copies of buses communicating the central processors with each of the other units. Each central processor includes a configuration control circuit which generates internal signals for determining the various bus configurations.
Inventors
- 👤 Dennis A Heck
- 👤 Rolfe E Buhrke
- 👤 John J Mele
- 👤 Verner K Rice
- 👤 Donald L Schulte
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:17
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1629; G06F11/1654; G06F11/1633; G06F11/165; H; H04; H04Q; H04Q3/00; H04Q3/42; H04Q3/54; H04Q3/545; H04Q3/54541; H04Q3/54558; G06F11/20; G06F11/2002; G06F11/2007
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
238 words
In a digital communications system having duplicate copies of central data processors wherein only one central processor is active at one time and the other is standby, and duplicate copies of storage means each having an associated bus means for communicating with both of said central processors, said bus means including a send bus for transmitting signals from said central processor to said storage means and a return bus for transmitting signals from said storage means to said central processors, the improvement comprising: configuration control circuit means only in each of said central processors including active unit bistable circuit means for governing which of said central processors is active and which is standby on a mutually exclusive basis; central processor trouble bistable circuit means responsive to program control signals and to internally sensed conditions for generating a trouble level signal representative of its associated central processor having sensed a malfunction therein for inhibiting the transmission of its associated central processor to said transmit bus upon detection of a malfunction; and central processor-storage means bus configuration control logic circuit means including storage means C bistable circuit means responsive to program signals and to internal malfunction signals for generating output signals defining which copy of said storage means bus means is primary and which is secondary; and combinatorial logic circuit means responsive to the output signals of said C bistable circuit means for generating separate multiple bus control output signals.
Claim 2
Dependent Claim
238 words
In a digital communications system having duplicate copies of central data processors wherein only one central processor is active at one time and the other is standby, and duplicate copies of storage means each having an associated bus means for communicating with both of said central processors, said bus means including a send bus for transmitting signals from said central processor to said storage means and a return bus for transmitting signals from said storage means to said central processors, the improvement comprising: configuration control circuit means only in each of said central processors including active unit bistable circuit means for governing which of said central processors is active and which is standby on a mutually exclusive basis; central processor trouble bistable circuit means responsive to program control signals and to internally sensed conditions for generating a trouble level signal representative of its associated central processor having sensed a malfunction therein for inhibiting the transmission of its associated central processor to said transmit bus upon detection of a malfunction; and central processor-storage means bus configuration control logic circuit means including storage means C bistable circuit means responsive to program signals and to internal malfunction signals for generating output signals defining which copy of said storage means bus means is primary and which is secondary; and combinatorial logic circuit means responsive to the output signals of said C bistable circuit means for generating separate multiple bus control output signals.
Claim 3
Dependent Claim
166 words
The system of claim 1 wherein said central processor-storage means bus configuration control logic circuit means further comprises storage means B bistable circuit means responsive to program signals for generating output signals for communicating both of said send buses of said storage means and both of said return buses of said storage means with the active copy of the central processor and for communicating both copies of said storage means return buses with said standby central processor while inhibiting transmission of said standby central processor, whereby said system may operate in a merged bus mode; and wherein said combinatorial logic circuit means is responsive to the output signals of said B bistable circuit means; and said system further comprises input-output circuit means responsive to said output signals of said combinatorial Logic circuitry for communicating the active central processor with both instruction storage send buses and both instruction-storage receive buses, and for communicating the standby central processor with both instruction storage receive buses in a merged mode.
Claim 4
Dependent Claim
86 words
The system of claim 1 wherein each of said central processors matches its own signals with those of the other central processor and generates error matching signal levels when a difference is detected, said improvement further comprising central processor separate bistable circuit means in each central processor for inhibiting the transmission of said error matching signals levels to the other central processor when in one state, and for enabling the transmission of said error matching signal levels to the other central processor when in another state.
Claim 5
Dependent Claim
17 words
The system of claim 3 wherein said central processor separate flip-flops are responsive to program controlled signals.
Claim 6
Dependent Claim
49 words
The system of claim 3 further comprising diagnostic bistable circuit means in each of said configuration control circuit means responsive to program controlled signals for generating signals permitting programmed diagnostic routines to be performed on its associated central processor when said associated central processor is in the standby state.
Claim 7
Dependent Claim
28 words
The system of claim 5 wherein the central processor separate bistable circuit means, when active, resets the diagnostic bistable circuit means of its associated configuration control circuit means.
Claim 8
Dependent Claim
50 words
The system of claim 2 further comprising in each configuration control circuit means, a central processor copy bistable circuit means for generating a signal representative of its associated central processor only, whereby a program being executed may sense which copy of the central processor is active and which is standby.
Claim 9
Dependent Claim
61 words
The system of claim 2 further comprising in each central processor-storage means bus configuration circuit means T bistable circuit means for generating a signal representative of an associated one of said storage means'' having detected a malfunction, and for inhibiting its associated B bistable circuit means to prevent communication of the active central processor with both copies of said storage means.
Claim 10
Dependent Claim
44 words
The system of claim 8 further comprising in each of said central processor-storage means bus configuration circuit means a D bistable circuit means for generating signals for controlling communication of its associated central processor with data bus means associated with said instruction storage means.
Claim 11
Dependent Claim
174 words
The system of claim 1 wherein said system further comprises duplicate copies of peripheral unit means for interfacing with a telephone network, each of said peripheral unit means having an associated bus means for communicating with both of said central processors, wherein the improvement further comprises: peripheral unit C bistable circuit means for generating signals for controlling which copy of said peripheral unit means is primary and which is secondary; peripheral unit B bistable circuit means for generating signals for permitting both of said peripheral unit means to communicate with the active central processor; and peripheral unit T bistable circuit means for generating a trouble signal level when a malfunction is detected in its associated peripheral unit means for inhibiting operation of its associated peripheral unit B bistable circuit means; and combinational logic circuit means receiving said output signals of said C, B and T bistable circuit means of said peripheral unit means for generating separate multiple bus control signals for selectively communicating predetermined ones of said peripheral unit buses with said central processor.
Claim 12
Dependent Claim
174 words
The system of claim 1 wherein said system further comprises duplicate copies of process store means for interfacing with a telephone network, each of said process store means having an associated bus means for communicating with both of said cenTral processors, wherein the improvement further comprises: process store C bistable circuit means for generating signals for controlling which copy of said process store means is primary and which is secondary; process store B bistable circuit means for generating signals for permitting both of said process store means to communicate with the active central processor; and process store T bistable circuit means for generating a trouble signal level when a malfunction is detected in its associated process store means for inhibiting operation of its associated process store B bistable circuit means; and combinational logic circuit means receiving said output signals of said C, B and T bistable circuit means of said process store means for generating separate multiple bus control signals for selectively communicating predetermined ones of said process store buses with said central processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |