Patent US3882426A successfully refreshed from Google Patents.
US3882426A
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Increment varying means for incremental encoder and decoder
Assignee: General Electric Co
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Filing: 1973-07-16
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Granted: 1975-05-06
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Expires: 1993-07-16
Abstract
Abstract In a digital incremental encoder or decoder for processing pulse signals whose logical significance indicates whether the timevarying amplitude information signal expressed by them has increased or decreased by more than a given quantum since the occurrence of the preceding pulse, the magnitude of the quantum is determined by an accumulating counter whose content is altered to approximate the absolute magnitude of the information signal amplitude change between successive pulses. By the present invention, the content of the accumulating counter is changed more slowly when the content is small than when it is large. This is done by permitting only a fraction of otherwise effective contentchanging control signals to affect the accumulating counter when its content is below a predetermined content.
Inventors
- 👤 Jr David F Hoeschele
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:14
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/02; H03M3/022
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
343 words
In apparatus for thE interconversion of a first representation of an information signal by a time-varying amplitude with a second representation of the same information signal by a succession of pulse signals each having one of two possible logical significances which represent the sign of the change in the amplitude of the first representation since the occurrence of the last preceding pulse signal of the second representation, which comprises: a source of clock pulses connected to herein subsequently recited pulse sequence analysis means, digital companding counter means, and adder means; pulse sequence analysis means to receive the said pulse signals in sequence and to produce responsively thereto a first pulse sequence output signal when a first predetermined number of pulses in the sequence are all of the same logical significance and a second pulse sequence output signal when a second predetermined number of pulses in the sequence are of alternate logical significance; digital companding counter means connected to be stepped to be increased in registration during the existence of a first pulse sequence output signal and to be decreased in registration during the existence of a second pulse sequence output signal; adder means connected to receive the registration of the companding counter means and, responsively to a pulse signal of the second representation of first logical significance to add, and responsively to a pulse signal of the second representation of second logical significance to subtract, the registration of the companding counter means to and from the content of digital storage means, which are connected to digital to analogue converter means whose output is the said first representation; the improvement which comprises: companding counter control means comprising: companding counter registration function means connected to registration outputs of the said companding counter, and, responsively thereto, to control stepping impulse control means to step the companding counter means at a maximum rate when the companding counter registration is greater than a predetermined value and to step the companding counter means at a lower rate when the companding counter registration is not greater than the predetermined value.
Claim 2
Dependent Claim
343 words
In apparatus for thE interconversion of a first representation of an information signal by a time-varying amplitude with a second representation of the same information signal by a succession of pulse signals each having one of two possible logical significances which represent the sign of the change in the amplitude of the first representation since the occurrence of the last preceding pulse signal of the second representation, which comprises: a source of clock pulses connected to herein subsequently recited pulse sequence analysis means, digital companding counter means, and adder means; pulse sequence analysis means to receive the said pulse signals in sequence and to produce responsively thereto a first pulse sequence output signal when a first predetermined number of pulses in the sequence are all of the same logical significance and a second pulse sequence output signal when a second predetermined number of pulses in the sequence are of alternate logical significance; digital companding counter means connected to be stepped to be increased in registration during the existence of a first pulse sequence output signal and to be decreased in registration during the existence of a second pulse sequence output signal; adder means connected to receive the registration of the companding counter means and, responsively to a pulse signal of the second representation of first logical significance to add, and responsively to a pulse signal of the second representation of second logical significance to subtract, the registration of the companding counter means to and from the content of digital storage means, which are connected to digital to analogue converter means whose output is the said first representation; the improvement which comprises: companding counter control means comprising: companding counter registration function means connected to registration outputs of the said companding counter, and, responsively thereto, to control stepping impulse control means to step the companding counter means at a maximum rate when the companding counter registration is greater than a predetermined value and to step the companding counter means at a lower rate when the companding counter registration is not greater than the predetermined value.
Claim 3
Dependent Claim
98 words
The improvement claimed in claim 1 in which: the companding counter registration function means comprises a buffer connected to receive as inputs the 1 outputs of at least one of the most significant digit stages of the companding counter means, and its output is connected to gate every stepping impulse to step the companding counter means, and the stepping impulse control means comprises stepping impulse counter means which count all stepping impulses but gate to the companding counter to step it only those stepping pulses which occur at a predetermined registration of the said stepping impulse counter means.
Claim 4
Dependent Claim
124 words
The improvement claimed in claim 2 in which: the companding counter registration function means comprises a plurality of buffers connected to receive as inputs the 1 outputs of differently significant adjacent groups of the most significant digit stages of the companding counter means; the output of the said buffer which is connected to receive as inputs the 1 outputs of the most significant stages of the companding counter means is connected to gate every stepping impulse to step the companding counter means; the output of any other buffer of the said plurality is connected to gate stepping pulses which occur at a predetermined registration of the stepping impulse counter means representative of less than the full counting capacity of the stepping impulse counter means.
Claim 5
Dependent Claim
47 words
The improvement claimed in claim 1 in which: the stepping impulse control means is connected to step the companding counter means by applying stepping pulses to a stage of greater significance than the least significant stage when the companding counter registration is greater Than a predetermined value.
Claim 6
Dependent Claim
37 words
The improvement claimed in claim 2 in which: the stepping impulse counter means are connected to be reset to a zero registration by all those pulses which are gated to the companding counter means to step it.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |