Hysteresis circuits using insulated gate field effect transistors

Claim 2

A hysteresis circUit comprising: an input means; an output means; first circuit means coupled to said input means and including a first switchable impedance means for generating control signals in response to input voltage levels; second circuit means including a second switchable impedance means for switching output voltage levels impressed on said output means in response to said control signals; voltage dividing circuit means connected between said input and output means; and third switchable impedance means connected in circuit with said first switchable impedance means for controlling input voltage levels switching output voltage levels in response to outputs from said voltage dividing circuit means; said third switchable impedance means is connected in series with said first switchable impedance means.

Claim 3

A hysteresis circuit according to claim 1 wherein said first, second and third switchable impedance means consist of insulated gate field effect transistors.

Claim 4

A hysteresis circuit according to claim 1 wherein said voltage dividing circuit means includes first and second impedance means.

Claim 5

A hysteresis circuit according to claim 3 wherein said first impedance means includes a fourth switchable impedance means which is rendered on in response to an input voltage level.

Claim 6

A hysteresis circuit according to claim 4 wherein said fourth switchable impedance means consists of an insulated gate field effect transistor.

Claim 7

A hysteresis circuit according to claim 1 wherein said first circuit means includes a first insulated gate field effect transistor whose gate is connected to said input means and a second field effect transistor whose drain and gate are jointly connected to a potential source and whose source is connected to the drain of said first field effect transistor; said second circuit means includes a third field effect transistor whose gate is connected to the junction of the drain of said first field effect transistor and the source of said second field effect transistor and whose source is connected to a referential potential point, and a fourth field effect transistor whose gate and drain are jointly connected to the potential source and whose source is connected to the drain of said third field effect transistor and to said output means; and said voltage dividing circuit means includes a fifth field effect transistor whose gate and drain are jointly connected to said input means and a sixth field effect transistor whose gate is connected to the potential source, whose source is connected to said output means and whose drain is connected to the source of said fifth field effect transistor; and said third switchable impedance means includes a seventh field effect transistor whose gate is connected to a voltage division point between the source of said fifth field effect transistor and the drain of said sixth field effect transistor, whose drain is connected to the source of said first field effect transistor and whose source is connected to the referential potential point.

Claim 8

A hysteresis circuit according to claim 6 wherein said voltage dividing circuit means includes an eighth field effect transistor whose source is connected to the voltage dividing point, whose drain is connected to the source of said fifth field effect transistor and whose gate is connected to the potential source.

Claim 9

A hysteresis circuit according to claim 6 wherein said voltage dividing circuit means includes an eighth field effect transistor whose source is connected to the voltage dividing point and whose drain and gate are jointly connected to the source of said fifth field effect transistor.

Claim 10

A hysteresis circuit using insulated gate field effect transistors each having drain, source and gate electrodes, said hysteresis circuit comprising: a potential source; input and output terminals; a first transistor having the gate connected to said input terminal; a second transistor having the gate and drain connected to said potential source and the source Connected to the drain of said first transistor; a third transistor having the drain connected to the source of said first transistor and the source connected to a reference potential point; a fourth transistor having the gate connected to the drain of said first transistor and the source connected to the reference potential point; a fifth transistor having the drain and gate connected to said potential source and the source connected to said output terminal and the drain of said fourth transistor; a sixth transistor having the drain and gate connected to said input terminal and the source connected to the gate of said third transistor; and a seventh transistor having the drain connected to the source of said sixth transistor, the source connected to said output terminal and the gate connected to said potential source.

Claim 11

A hysteresis circuit using insulated gate field effect transistors each having drain, source and gate electrodes, said hysteresis circuit comprising: a potential source; input and output terminals; a first transistor having the gate connected to said input terminal; a second transistor having the gate and drain connected to said potential source and the source Connected to the drain of said first transistor; a third transistor having the drain connected to the source of said first transistor and the source connected to a reference potential point; a fourth transistor having the gate connected to the drain of said first transistor and the source connected to the reference potential point; a fifth transistor having the drain and gate connected to said potential source and the source connected to said output terminal and the drain of said fourth transistor; a sixth transistor having the drain and gate connected to said input terminal and the source connected to the gate of said third transistor; and a seventh transistor having the drain connected to the source of said sixth transistor, the source connected to said output terminal and the gate connected to said potential source.

Claim 12

A hysteresis circuit using insulated gate field effect transistors each having drain, source and gate electrodes, said hysteresis circuit comprising: a potential source; input and output terminals; a first transistor having the gate connected to said input terminal; a second transistor having the gate and drain connected to said potential source, and the source connected to the drain of said first transistor; a third transistor having the drain connected to the source of said first transistor and the source connected to a reference potential point; a fourth transistor having the gate connected to the drain of said first transistor and the source connected to the reference potential point; a fifth transistor having the drain and gate connected to said potential source and the source connected to said output terminal and the drain of said fourth transistor; a sixth transistor having the drain and gate connected to said input terminal; a seventh transistor having the drain connected to the source of said sixth transistor, the gate connected to said potential source and the source connected to the gate of said third transistor; and an eighth transistor having the source connected to said output terminal, the gate connected to said potential source and the drain connected to the source of said seventh transistor.

Claim 13

A hysteresis circuit using insulated gate field effect transistors each having drain, source and gate electrodes, said hysteresis circuit comprising: a potential source; input and output terminals; a first transistor having the gate connected to said input terminal; a second transistor having the gate and drain connected to said potential source, and the source connected to the drain of said first transistor; a third transistor having the drain connected to the source of said first transistor and the source connected to a reference potential point; a fourth transistor having the gate connected to the drain of said first transistor and the source connected to the reference potential point; a fifth transistor having the drain and gate connected to said potential source and the source connected to said output terminal and the drain of said fourth transistor; a sixth transistor having the drain and gate connected to said input terminal; a seventh transistor having the drain connected to the source of said sixth transistor, the gate connected to said potential source and the source connected to the gate of said third transistor; and an eighth transistor having the source connected to said output terminal, the gate connected to said potential source and the drain connected to the source of said seventh transistor.

Claim 14

A hysteresis circuit using insulated gate field effect transistors each having drain, source and gate electrodes, said hysteresis circuit comprising: a potential source; input and output terminals; a first transistor having the gate connected to said input terminal; a second transistor having the gate and drain connected to said potential source, and the source connected to the drain of said first transistor; a third transistor having the drain connected to the source of said first transistor and the source connected to a reference potential point; a fourth transistor having the gate connected to the drain of said first transistor and the source connected to the reference potential point; a fifth transistor having the drain and gate connected to said potential source and the source connected to said output terminal and the drain of said fourth transistor; a sixth transistor having the drain and gate connected to said input terminal; a seventh transistor having the drain and gate connected to the source of said sixth transistor, and the source connected to the gate of said third transistor; and an eighth transistor having the source connected to said output terminal, the gate connected to said potential source and the drain connected to the source of said seventh transistor.

Claim 15

A hysteresis circuit using insulated gate field effect transistors each having drain, source and gate electrodes, said hysteresis circuit comprising: a potential source; input and output terminals; a first transistor having the gate connected to said input terminal; a second transistor having the gate and drain connected to said potential source, and the source connected to the drain of said first transistor; a third transistor having the drain connected to the source of said first transistor and the source connected to a reference potential point; a fourth transistor having the gate connected to the drain of said first transistor and the source connected to the reference potential point; a fifth transistor having the drain and gate connected to said potential source and the source connected to said output terminal and the drain of said fourth transistor; a sixth transistor having the drain and gate connected to said input terminal; a seventh transistor having the drain and gate connected to the source of said sixth transistor, and the source connected to the gate of said third transistor; and an eighth transistor having the source connected to said output terminal, the gate connected to said potential source and the drain connected to the source of said seventh transistor.