Absolute value circuit employing opposite conductivity type switches

Claim 2

A circuit comprising: at least one input terminal adapted for connection to a source of input signals; a signal comparator means responsive to said input signals and to a reference signal level for providing one control signal when the input signal is at one polarity relative to said reference signal level and a second control signal when the input signal is at another polarity relative to said reference signal level; first and second semiconductor switching devices of opposite conductivity types, said first device being responsive to said one control signal for providing one low impedance signal path for said one polarity of the input signal, said second device being responsive to said second control signal for providing another low impedance signal path for said other polarity of input signal; and signal translation means coupled to said first and second devices for inverting the polarity oF the signal provided via said one low impedance path and for maintaining the polarity of the signal provided via said other low impedance path, said signal translation means providing an output signal substantially equal to the absolute value of the input signal.

Claim 3

The circuit according to claim 1 wherein said first and second semiconductor switching devices comprise N-channel and P-channel MOS transistors, respectively.

Claim 4

The circuit according to claim 2 wherein said signal translation means comprises an operational amplifier having an inverting input terminal connected to the low impedance path provided by said first device and a non-inverting input terminal connected to the low impedance path provided by said second device.

Claim 5

The circuit according to claim 3 further comprising a polarity indicating means responsive to said first and second control signals for providing an indication of the polarity of said input signal.

Claim 6

A circuit comprising: a pair of circuit input terminals adapted for connection to a source of input signals; a signal comparator having first and second input terminals and an output terminal, said first comparator input terminal being connected to one of said circuit input terminals, said second comparator input terminal being connected to a point of reference potential and to said other circuit input terminal, said signal comparator providing a first control voltage level at said comparator output terminal when the voltage at said first input terminal of said comparator is positive with respect to said reference potential and a second control voltage level at said comparator output terminal when the voltage at said first input terminal of said comparator is negative with respect to said reference level; first and second normally closed semiconductor switching devices of opposite conductivity types, each having first and second main electrodes and a control electrode, the control electrode of said first and said second device being connected to said comparator output terminal, one main electrode of said first and of said second device being connected to said one of said circuit input terminals, said first device providing a low impedance path for said input signals in response to said first control voltage level and said second device providing a low impedance path for said input signals in response to said second control voltage level; and a signal translation means having a pair of input terminals and an output terminal, one input terminal of said translation means being connected to the other main electrode of said first device, the other input terminal of said translation means being connected to the other main electrode of said second device, said signal translating means operative to pass input signals of a given polarity and to invert the polarity of input signals having a polarity opposite the given polarity, whereby the signals provided at the output terminal of said translation means are substantially equal to the absolute value of the input signals.

Claim 7

A circuit comprising: a pair of circuit input terminals adapted for connection to a source of input signals; a signal comparator having first and second input terminals and an output terminal, said first comparator input terminal being connected to one of said circuit input terminals, said second comparator input terminal being connected to a point of reference potential and to said other circuit input terminal, said signal comparator providing a first control voltage level at said comparator output terminal when the voltage at said first input terminal of said comparator is positive with respect to said reference potential and a second control voltage level at said comparator output terminal when the voltage at said first input terminal of said comparator is negative with respect to said reference level; first and second normally closed semiconductor switching devices of opposite conductivity types, each having first and second main electrodes and a control electrode, the control electrode of said first and said second device being connected to said comparator output terminal, one main electrode of said first and of said second device being connected to said one of said circuit input terminals, said first device providing a low impedance path for said input signals in response to said first control voltage level and said second device providing a low impedance path for said input signals in response to said second control voltage level; and a signal translation means having a pair of input terminals and an output terminal, one input terminal of said translation means being connected to the other main electrode of said first device, the other input terminal of said translation means being connected to the other main electrode of said second device, said signal translating means operative to pass input signals of a given polarity and to invert the polarity of input signals having a polarity opposite the given polarity, whereby the signals provided at the output terminal of said translation means are substantially equal to the absolute value of the input signals.

Claim 8

The circuit according to claim 5 further comprising a polarity indicator means connected to said comparator output terminal and responsive to said first and to said second control voltage levels for indicating the polarity of the input signal.

Claim 9

The circuit according to claim 5 wherein said signal comparator comprises an operational amplifier having an inverting input terminal connected to said one circuit input terminal and a non-inverting input terminal connected to said point of reference potential.

Claim 10

The circuit according to claim 5 further comprising: a first resistor connected between the other main electrode of said second device and the other input terminal of said signal translation means; and a second resistor connected between the other main electrode of said first device and said point of reference potential; said first and second resistors having resistance values such that the input impedance of said circuIt remains the same for input signals of said given polarity and for input signals of a polarity opposite the given polarity.

Claim 11

The circuit according to claim 8 wherein said first and second resistors have equal resistance values.

Claim 12

The circuit according to claim 9 further comprising a third resistor connected between said other main electrode of said first device and said one input terminal of said signal translation means.

Claim 13

The circuit according to claim 7 wherein said first device comprises a P-channel MOS transistor and said second device comprises an N-channel MOS transistor.

Claim 14

The circuit according to claim 11 wherein said signal translation means comprises a second operational amplifier having an inverting input terminal connected to the other main electrode of said N-channel device and a non-inverting input terminal connected to the other main electrode of said P-channel device, said second operational amplifier being operative to provide a signal substantially equal to the absolute value of said input signal at the output terminal thereof.