Patent US3881175A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3881175A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit SOS memory subsystem and method of making same

Assignee: LSI Systems Inc
•
Filing: 1973-12-26
•
Granted: 1975-04-29
•
Expires: 1993-12-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An integrated circuit silicon-on-sapphire memory subsystem and the method of making same is disclosed. The subsystem comprises an insulating sapphire substrate, an array of memory circuits disposed on one surface of the substrate, a bus system disposed on the substrate for carrying electrical signals and power from a power source to selected ones of the memory circuits, and a plurality of fuses, each fuse comprised of a semiconductive material and interconnecting the bus system to a selected memory circuit. In order to determine which of the array of memory circuits are selected to be part of the memory subsystem, the operability of the memory circuits is tested. If a memory circuit is found unacceptable, the fuse connecting it to the bus system is blown so as to electrically isolate that memory circuit from the acceptable memory circuits.

Inventors

  • 👤 Frank M Wanlass

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 12:33
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83; G11C29/832; G11C5/00; H; H10; H10B; H10B99/00; H10B99/10

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 49 words
AN INTEGRATED CIRCUIT SOS MEMORY SUBSYSTEM COMPRISING: AN INSULATING SAPPHIRE SUBSTRATE, AN ARRAY OF MEMORY CIRCUITS DISPOSED ON ONE SURFACE OF SAID SUBSTRATE, A BUS SYSTEM DISPOSED OVER SAID SUBSTRATE, AND A PLURALITY OF FUSES FOR SELECTIVELY ELECTRICALLY INTERCONNECTING SAID BUS SYSTEM TO ONE OF A PREDETERMINED NUMBER OF
Claim 2
Dependent Claim 49 words
AN INTEGRATED CIRCUIT SOS MEMORY SUBSYSTEM COMPRISING: AN INSULATING SAPPHIRE SUBSTRATE, AN ARRAY OF MEMORY CIRCUITS DISPOSED ON ONE SURFACE OF SAID SUBSTRATE, A BUS SYSTEM DISPOSED OVER SAID SUBSTRATE, AND A PLURALITY OF FUSES FOR SELECTIVELY ELECTRICALLY INTERCONNECTING SAID BUS SYSTEM TO ONE OF A PREDETERMINED NUMBER OF
Claim 3
Dependent Claim 58 words
An integrated circuit SOS memory subsystem as recited in claim 1 wherein said bus system comprises a plurality of conductive buses and wherein each said memory circuit includes a plurality of conductive test pads, one of said fuses interconnecting one of said buses to one of said test pads for each of said predetermined number of memory circuits.
Claim 4
Dependent Claim 25 words
An integrated circuit SOS memory subsystem as recited in claim 1 wherein each fuse has a resistance of between 10 and 100 ohms per square.
Claim 5
Dependent Claim 27 words
An integrated circuit SOS memory subsystem as recited in claim 1 and further including means coating the exposed surfaces of said substrate for protecting said memory subsystem.
Claim 6
Dependent Claim 70 words
An integrated circuit SOS memory subsystem as recited in claim 2 wherein said plurality of conductive buses includes a first set of buses, each bus of said first set being spaced-apart from and parallel to adjacent buses, said first set extending outside the outermost column of said array, and terminals for said buses lying in a plane along one edge of said substrate for connecting to a printed circuit socket.
Claim 7
Dependent Claim 54 words
An integrated circuit SOS memory subsystem as recited in claim 5 wherein said plurality of conductive buses includes a second set of buses that are coplanar with and extend substantially perpendicular to said first set, and further including fuses for interconnecting a bus of said first set to a bus of said second set.
Claim 8
Dependent Claim 32 words
An integrated circuit SOS memory subsystem as recited in claim 6 wherein said fuses are disposed on said one surface of said substrate and are beneath the plane of said bus system.

References Cited (Backward Citations)

US3529299A Cited
US3584183A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-04-28 1978-10-28 1979-04-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-04-28 1982-10-28 1983-04-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-04-28 1986-10-28 1987-04-29 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag