Condition code determination and data processing

Claim 2

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus, and operative in response to instructions having operation codes for specifying operations to be executed and having operand fields for identifying operands to be utilized in executing the operations, and additional apparatus comprising, instruction sequence processing means for processing instructions including a branch instruction specifying one of a plurality of possible instruction streams to be taken in accordance with a condition code specified by said branch instruction, and including a condition code-setting instruction specifying operands to be utilized in executing the condition code-setting instructions, comparator means for comparing the operands specified by said condition code-setting instruction to form a comparison result, means responsive to the operation code of said condition codesetting instruction in said instruction sequence processing means and to said comparison result in said comparator means for setting said condition code without the necessity of waiting for the execution of the operation specified by the operation code of said code-setting instruction.

Claim 3

The data processing system of claim 1 wherein said comparator means includes means for comparing said operands on a bit-by-bit basis to detect the first bit position, from high-order to low-order, having a pre-determined equality relationship.

Claim 4

The data processing system of claim 1 where said instruction sequence processing means includes a plurality of stages, means for introducing a plurality of segmented instructions into said stages with a time-offset between instructions equal to an integral number of clock cycles, and wherein each of said instructions includes a plurality of one-cycle segments, said segments including PFO for prefetch-offset formation, IA for instruction address formation, IB1 for instruction buffer access initiation IB2 for instruction buffer access completion, D for instruction decoding, R for reading address data, OA for operand address formation, OB1 for operand buffer access initiation, OB2 for operand buffer access completion, E1 for execution initiation, E2 for execution completion, CK for checking, W for writing, and wherein said means responsive includes means is operative to set said condition code at the completion of said E1 cycle.

Claim 5

The data processing system of claim 1 wherein said instruction execution apparatus includes a first functional unit for comparing said operands during one cycle of said data processing system and includes a second functional unit for executing instructions over a subsequent one cycle of the data processing system, said time-offset of instructions in said instruction sequence processing means being equal to the cycle time for data manipulations in said first and second functional units.

Claim 6

The data processing system of claim 2 wherein said pre-determined equality relationship is identity of bits.

Claim 7

The data processing system of claim 2 wherein said pre-determined equality relationship is non-identity of bits.

Claim 8

The data processing system of claim 3 wherein said instruction sequence processing means includes first and second register means for storing a first operand and a second operand specified by said condition code-setting instruction, and including means for storing the operation code of said condition code-setting instruction.

Claim 9

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus, and additional apparatus comprising, instruction sequence processing means for processing instructions in an instruction stream including a branch instruction specifying a branch point wherein, at said branch point, the instruction stream branches to a targeted path of instructions if a condition code specified by the branch instruction is set or follows a non-branch path of instructions if said condition code is not set and wherein the condition code is set or not set responsive to a condition code-setting instruction contained within the instruction stream at a point prior to said branch point, said condition code-setting instruction including fields specifying an operation code and the location of first and second operands to be processed in the manner defined by the operation code, comparator means for comparing the first and second operands of the code-setting instruction to detect equality relationships, control means including decoder means for decoding the operation coDe of said code-setting instruction to select a pre-determined equality relationship in said comparator means for responsively controlling the setting of the condition code.

Claim 10

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus, and additional apparatus comprising, instruction sequence processing means for processing instructions in an instruction stream including a branch instruction specifying a branch point wherein, at said branch point, the instruction stream branches to a targeted path of instructions if a condition code specified by the branch instruction is set or follows a non-branch path of instructions if said condition code is not set and wherein the condition code is set or not set responsive to a condition code-setting instruction contained within the instruction stream at a point prior to said branch point, said condition code-setting instruction including fields specifying an operation code and the location of first and second operands to be processed in the manner defined by the operation code, comparator means for comparing the first and second operands of the code-setting instruction to detect equality relationships, control means including decoder means for decoding the operation coDe of said code-setting instruction to select a pre-determined equality relationship in said comparator means for responsively controlling the setting of the condition code.

Claim 11

The data processing system of claim 8 wherein said operands are positive or negative and are expressed in floating point or fixed point arithmetic and wherein said comparator means includes means for comparing each bit in one of said operands with the corresponding bit in the other of said operands in order to detect the first occurrence, proceeding from the highest order toward the lowest order bits, of a pre-determined equality relationship.

Claim 12

The data processing system of claim 8 wherein said instruction sequence processing means includes a plurality of stages, means for introducing a plurality of segmented instructions into said stages with a time-offset between instructions equal to an integral number of clock cycles, and wherein each of said instructions includes a plurality of one-cycle segments, said segments including PFO for prefetch-offset formation, IA for instruction address formation, IB1 for instruction buffer access initiation, IB2 for instruction buffer access completion, D for instruction decoding, R for reading address data, OA for operand address formation, OB1 for operand buffer access initiation, OB2 for operand buffer access completion, E1 for execution initiation, E2 for execution completion, CK for checking, W for writing, and wherein said control means includes means operative to set said condition code at the completion of the E1 cycle of the code-setting instruction.

Claim 13

The data processing system of claim 10 wherein the instruction execution apparatus includes said comparator means as a first functional unit for comparing said operands during one cycle of said data processing system and includes a second functional unit for executing instructions over a subsequent one cycle of the data processing system, said time-offset of instructions in said instruction sequence processing means being equal to the cycle time for data manipulations in said first and second functional units.

Claim 14

The data processing system of claim 8 wherein, for operands in fixed point arithmetic, said equality relationship is identity of bits when one of said operands is positive in binary notation and the other of said operands is negative in 2''s complement notation.

Claim 15

The data processing system of claim 8 wherein, for operands in fixed point arithmetic, said equality relationship is non-identity of bits when both operands are positive in binary notation or both operands are negative in 2''s complement notation.

Claim 16

The data processing system of claim 8 wherein, for operands in floating point arithmetic, said equality relationship is non-identity of corresponding bits excluding the sign bits.

Claim 17

The data processing system of claim 13 wherein the comparator means functions to determine that the first and second operands are equal if all corresponding bits in each operand are identical.

Claim 18

The data processing system of claim 13 wherein, for positive operands, the absolute value of the operand having a 1 in the first non-identical bit position is greater than the absolute value of the operand having a 0 in the corresponding bit position.

Claim 19

A data processing system of claim 13 wherein, for negative operands, the absolute value of the operand having a 0 in the first non-identical bit position is greater than the absolute value of the operand having a 1 in the corresponding bit position.

Claim 20

The data processing system of claim 14 wherein the absolute value of the operand having a 1 in the first non-identical bit position is greater than the absolute value of the operand having a 0 in the corresponding bit position.

Claim 21

The data processing system of claim 12 wherein none of the corresponding bits are identical, the absolute value of the positive operand is less than the absolute value of the negative operand.

Claim 22

The data processing system of claim 12 wherein, if the first identical corresponding bits are 0''s the absolute value of the positive operand is less than the absolute value of the negative operand.

Claim 23

The data processing system of claim 12 wherein, if the first identical corresponding bits are 1''s, the absolute value of the positive operand is greater than or equal to the absolute value of the negative operand.

Claim 24

The data processing system of claim 12 wherein, if the first identical corresponding bits are 1''s and all lower-order bits are 0''s, the positive operand is identically equal to the negative operand.

Claim 25

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus where said instruction handling apparatus includes instruction processing means for processing instructions of an instruction stream wherein, at a branch point, the instruction stream branches to a targeted path if a condition code is set or follows a non-branch path if a condition code is not set and wherein the condition code is set or not responsive to a condition code-setting instruction contained within the instruction stream prior to the branch point, said condition code-setting instruction including fields specifying an operation code and the location of first and second operands to be processed in the manner specified by the operation code to execute the code-setting instruction, said operands being positive or negative and expressed in floating point or fixed point arithmetic, said instruction sequence processing means including a plurality of stages, means for introducing a plurality of segmented instructions of the instruction stream into said stages with a time-offset between instructions equal to an integral number of clock cycles and wherein each of the instructions includes a plurality of one-cycle segments, said segments including PFO for prefetch-offset formation, IA for instruction address formation, IB1 for instruction buffer access initiation, IB2 for instruction buffer access completion, D for instruction decoding, R for reading address data, OA for operand address formation, OB1 for operand buffer access initiation, OB2 for operand buffer access completion, E1 for execution initiation, E2 for execution completion, CK for checking and W for writing, said system further including, comparator means for comparing the first and second operands of the code-setting instruction on a bit-by-bit basis to detect the first bit position, from high-order to low-order, having a pre-determined equality relationship of identity for one positive and one negative operand and having a pre-determined equality relationship of non-identity for both operands positive or both operands negative in fixed point arithmetic and for all operands in floating point arithmetic, and decoder and control means for selecting the predetermined equality relationship of identity on non-identity by decoding the operation code of the condition code-setting instruction.

Claim 26

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus where said instruction handling apparatus includes instruction processing means for processing instructions of an instruction stream wherein, at a branch point, the instruction stream branches to a targeted path if a condition code is set or follows a non-branch path if a condition code is not set and wherein the condition code is set or not responsive to a condition code-setting instruction contained within the instruction stream prior to the branch point, said condition code-setting instruction including fields specifying an operation code and the location of first and second operands to be processed in the manner specified by the operation code to execute the code-setting instruction, said operands being positive or negative and expressed in floating point or fixed point arithmetic, said instruction sequence processing means including a plurality of stages, means for introducing a plurality of segmented instructions of the instruction stream into said stages with a time-offset between instructions equal to an integral number of clock cycles and wherein each of the instructions includes a plurality of one-cycle segments, said segments including PFO for prefetch-offset formation, IA for instruction address formation, IB1 for instruction buffer access initiation, IB2 for instruction buffer access completion, D for instruction decoding, R for reading address data, OA for operand address formation, OB1 for operand buffer access initiation, OB2 for operand buffer access completion, E1 for execution initiation, E2 for execution completion, CK for checking and W for writing, said system further including, comparator means for comparing the first and second operands of the code-setting instruction on a bit-by-bit basis to detect the first bit position, from high-order to low-order, having a pre-determined equality relationship of identity for one positive and one negative operand and having a pre-determined equality relationship of non-identity for both operands positive or both operands negative in fixed point arithmetic and for all operands in floating point arithmetic, and decoder and control means for selecting the predetermined equality relationship of identity on non-identity by decoding the operation code of the condition code-setting instruction.

Claim 27

In a data processing system having a storage apparatus, instruction handling apparatus and instruction execution apparatus and operative in response to instructions having operation codes for specifying operations to be executed and having operand fields for identifying operands to be utilized in executing the operation codes, the method comprising the steps of, processing instruction sequences including a branch instruction specifying one of a plurality of possible instruction streams selected in accordance with a condition code specified by said branch instruction and including a condition code-setting instruction for setting said condition code and specifying operands to be utilized in executing the condition code-setting instruction, setting the condition code by comparing the operation code of said condition code-setting instruction and comparing the operands specified in said code-setting instruction without the necessity of waiting for the execution of the operation code in said code-setting instruction.

Claim 28

In a data processing system having a storage apparatus, instruction handling apparatus and instruction execution apparatus and operative in response to instructions having operation codes for specifying operations to be executed and having operand fields for identifying operands to be utilized in executing the operation codes, the method comprising the steps of, processing instruction sequences including a branch instruction specifying one of a plurality of possible instruction streams selected in accordance with a condition code specified by said branch instruction and including a condition code-setting instruction for setting said condition code and specifying operands to be utilized in executing the condition code-setting instruction, setting the condition code by comparing the operation code of said condition code-setting instruction and comparing the operands specified in said code-setting instruction without the necessity of waiting for the execution of the operation code in said code-setting instruction.

Claim 29

The method of claim 24 further including the steps of, comparing each bit in one of said operands with the corresponding bit in the other of said operands in order to detect the first occurrence of a pre-determined equality relationship proceeding from the highest-order toward the lowest-order bits.

Claim 30

The method of claim 25 further including the steps of, decoding the operation code of the condition code-setting instruction to select the pre-determined equality relationship.

Claim 31

The method of claim 26 further including the steps of comparing said first and second operands on a bit-by-bit basis to detect the first bit position, from highest-order toward lowest-order, to detect non-identity if said operation code indicates that said first and second operands are in floating point arithmetic, to detect non-identity if said operation code indicates said first and second operands are both positive or are both negative and are in fixed point arithmetic, and to detect identity if said operation code indicates said operands are in fixed point arithmetic and one operand is positive and the other operand is negative.

Claim 32

The data processing system of claim 8 wherein the setting of the condition code signifies a magnitude comparison of the first and second operands.

Claim 33

The data processing system of claim 8 wherein the setting of the condition code signifies an overflow condition resulting from the addition of or the substraction of the first and second operands.

Claim 34

The data processing system of claim 1 wherein said instruction sequence processing means includes means for processing a condition code-setting instruction and a branch instruction offset in time from said condition code-setting instruction whereby said branch instruction addresses a targeted instruction and wherein said targeted instruction is accessed if said condition code is set.

Claim 35

The data processing system of claim 30 wherein said means responsive operates as a function of the sign of the operands, of the type of arithmetic of the operands, and of the operation to be executed.

Claim 36

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus wherein the system performs data manipulations under the control of instructions having operation codes for specifying operations to be executed and having operand fields for identifying operands to be utilized in executing the operation codes, and where instructions are processed in segments where each segment has a duration equal to one or more clock cycles, and additional apparatus comprising, clock means providing clock signals which define clock cycles for controlling the data processing system, instruction sequence processing means for processing instructions including a branch instruction specifying one of a plurality of possible instruction streams to be taken in accordance with a condition code specified by said branch instruction, and including a condition code-setting instruction specifying operands to be utilized in executing the condition code-setting instructions, said instruction sequence processing means including a plurality of stages for storing instruction fields, means for sequentially stepping a plurality of said instructions through said stages with a time-offset between consecutive instructions, comparator means for comparing the operands specified by said condition code-setting instruction to form a comparison result, means responsive to the operation code of said condition code-setting instruction from one of said plurality of stages prior to execution of the operation specified by the operation code of said code-setting instruction in said instruction sequence processing means and to said comparison result in said comparator means for setting said condition code without the necessity of waiting For the execution of the operation specified by the operation code of said code-setting instruction.

Claim 37

A data processing system having storage apparatus, instruction handling apparatus and instruction execution apparatus wherein the system performs data manipulations under the control of instructions having operation codes for specifying operations to be executed and having operand fields for identifying operands to be utilized in executing the operation codes, and where instructions are processed in segments where each segment has a duration equal to one or more clock cycles, and additional apparatus comprising, clock means providing clock signals which define clock cycles for controlling the data processing system, instruction sequence processing means for processing instructions including a branch instruction specifying one of a plurality of possible instruction streams to be taken in accordance with a condition code specified by said branch instruction, and including a condition code-setting instruction specifying operands to be utilized in executing the condition code-setting instructions, said instruction sequence processing means including a plurality of stages for storing instruction fields, means for sequentially stepping a plurality of said instructions through said stages with a time-offset between consecutive instructions, comparator means for comparing the operands specified by said condition code-setting instruction to form a comparison result, means responsive to the operation code of said condition code-setting instruction from one of said plurality of stages prior to execution of the operation specified by the operation code of said code-setting instruction in said instruction sequence processing means and to said comparison result in said comparator means for setting said condition code without the necessity of waiting For the execution of the operation specified by the operation code of said code-setting instruction.