Phase locked loop clocking system

Claim 2

A phase locked loop clocking system for phase locking a clock signal with respect to an input signal consisting of a series of dipulses wherein each dipulse consists of two oppositely signed pulses, said phase locked loop clocking system comprising: means for detecting a point occurring between the peaks of the first and second pulses of each dipulse; means for generating a reference signal in response to the detected points; means for detecting a phase difference between said reference signal and said clock signal; and means for controlling the frequency of the clock signal so as to increase or decrease the frequency of the clock signal in response to the detected phase difference.

Claim 3

A phase locked loop clocking system for phase locking a clock signal with respect to an input signal consisting of a series of dipulses wherein each dipulse consists of two oppositely signed pulses, said phase locked loop clocking system comprising: means for detecting a point occurring between the peaks of the first and second pulses of each dipulse; means for generating a reference signal in response to the detected points; means for detecting a phase difference between said reference signal and said clock signal; and means for controlling the frequency of the clock signal so as to increase or decrease the frequency of the clock signal in response to the detected phase difference.

Claim 4

A phase locked loop clocking system for phase locking a clock signal with respect to an input signal consisting of a series of dipulses wherein each dipulse consists of two oppositely signed pulses, said phase locked loop clocking system comprising: means for detecting a point occurring between the peaks of the first and second pulses of each dipulse; means for generating a reference signal in response to the detected points; means for detecting a phase difference between said reference signal and said clock signal; and means for controlling the frequency of the clock signal so as to increase or decrease the frequency of the clock signal in response to the detected phase difference.

Claim 5

The apparatus of claim 1 wherein said means for detecting a point occurring between the peaks of said first and second pulses comprises: positive threshold detection means for detecting when a dipulse exceeds a positive threshold amplitude, said positive threshold detection means being operative to generate a threshold pulse during the time in which the amplitude of the dipulse exceeds the positive threshold amplitude; and negative threshold detection means for detecting when a dipulse exceeds a negative threshold amplitude, said negative threshold detection means being operative to generate a threshold pulse during the time in which the amplitude of the dipulse exceeds the negative threshold amplitude.

Claim 6

Th apparatus of claim 2 wherein said means for detecting a point occurring between the peaks of said first and second pulses further comprises: means for selecting the threshold pulse output from only one of said threshold detection means during the occurrence of any one dipulse, and means for generating a train of selected threshold pulses wherein each selected threshold pulse defines a point on each dipulse occurring between the peaks of the first and second pulses of each dipulse.

Claim 7

The apparatus of claim 3 wherein the series of dipulses in the input signal comprises two types of dipulses, the first type of dipulse consisting of a first positively signed pulse followed by a second negatively signed pulse, the second type of dipulse consisting of a first negatively signed pulse followed by a second positively signed pulse, and said means for selecting the threshold pulse output from only one of the threshold detection means during the occurrence of any one dipulse comprises: first gating means for gating the threshold pulse output of the positive threshold detection means, means for enabling said first gating means during the occurrence of the second type of dipulse whereby the threshold pulse output from the positive threshold detection means is selected each time a second type of dipulse occurs, second gating means for gating the threshold pulse output of the negative threshold detection means, and means for enabling said second gating means during the occurrence of the first type of dipulse whereby the threshold pulse output from the positive threshold detection means is selected each time a first type of dipulse oCcurs.

Claim 8

The apparatus of claim 4 wherein said means for enabling said first gating means during the occurrence of the second type of dipulse comprises: means for gating the threshold pulse output from the negative threshold detection means during the occurrence of the second type of dipulse; and means for generating an enabling pulse in response to the gated threshold pulse output from the negative threshold detection means, and wherein said means for enabling said second gating means during the occurrence of the first type of dipulse comprises: means for gating the threshold pulse output from the positive threshold detection means during the occurrence of the first type of dipulse, and means for generating an enabling pulse in response to the gated threshold pulse output from the positive threshold detection means.

Claim 9

The apparatus of claim 5 wherein each of said means for generating an enabling pulse comprises a one shot circuit which generates an output pulse that is equal to or greater than the time remaining in the then occurring dipulse.

Claim 10

The apparatus of claim 6 wherein said means for generating a reference signal in response to the detected points comprises: means for generating a train of reference pulses wherein each reference pulse occurs in response to each selected threshold pulse in the train of selected threshold pulses from said means for generating a train of selected threshold pulses.

Claim 11

The apparatus of claim 7 wherein the train of reference pulses from said means for generating a train of reference pulses is applied to said means for detecting a phase difference between the clock signal and the reference signal, and wherein said means for detecting a phase difference comprises: means for generating a phase lead pulse in response to a clock pulse in the clock signal terminating prior to the termination of a reference pulse in the reference signal, and means for generating a phase lag pulse in response to a reference pulse in the reference signal terminating prior to the termination of a clock pulse in the clock signal.

Claim 12

The apparatus of claim 8 wherein said means for generating a phase lead pulse comprises: first means for gating the reference signal with the negation of the clock signal, and means for enabling said first gating means only when the clock signal leads the reference signal, and wherein said means for generating a phase lag pulse comprises: second means for gating the clock signal with the negation of the reference signal, and means for enabling said second gating means when the clock signal lags the reference signal.

Claim 13

The apparatus of claim 9 wherein said means for enabling said first gating means when the clock signal leads the reference signal comprises: a pair of cross coupled NAND gates, wherein the first NAND gate receives the reference signal and the second NAND gate receives the negation of te clock signal, the output of said second NAND gate being applied to said first gating means; and said means for enabling said gating means when the clock signal lags the reference signal comprises: a pair of cross coupled NAND gates, wherein the first NAND gate receives the clock signal and the second NAND gate receives the negation of the reference signal, the output of said second NAND gate being applied to said second gating means.

Claim 14

The apparatus of claim 1 wherein said means for detecting a phase difference between the reference signal and the clock signal comprises: first phase difference detecting means for gating the clock signal with the negation of the reference signal; means for enabling said first phase difference detecting means when the clock signal lags the reference signal; second phase difference detecting means for gating the reference signal with the negation of the clock signal; and means for enabling said second phase difference detecting means when the clock signal leads sAid reference signal.

Claim 15

the apparatus of claim 11 wherein said means for enabling said first phase difference detecting means comprises; a pair of cross coupled NAND gates, wherein the first NAND gate receives the reference signal and the second NAND gate receives the negation of the clock signal, the output of said second NAND gate being applied to said first phase difference detecting means; and said means for enabling said second phase difference detecting means comprises; a pair of cross coupled NAND gates, wherein the first NAND gate receives the clock signal and the second NAND gate receives the negation of the reference signal, the output of said second NAND gate being applied to said second phase difference detecting means.

Claim 16

In a phase locked loop clocking system wherein a voltage controlled oscillator generates a clock signal comprising a train of clock pulses that are phase locked with respect to a reference signal having reference pulses of a fixed pulse width, apparatus for detecting a phase difference between the clock signal and the reference signal only when a reference pulse is present in the reference signal comprising: means for generating a phase lead pulse in response to a clock pulse terminating prior to the termination of a reference pulse, and means for generating a phase lag pulse in response to a reference pulse terminating prior to the termination of a clock pulse.

Claim 17

In a phase locked loop clocking system wherein a voltage controlled oscillator generates a clock signal comprising a train of clock pulses that are phase locked with respect to a reference signal having reference pulses of a fixed pulse width, apparatus for detecting a phase difference between the clock signal and the reference signal only when a reference pulse is present in the reference signal comprising: means for generating a phase lead pulse in response to a clock pulse terminating prior to the termination of a reference pulse, and means for generating a phase lag pulse in response to a reference pulse terminating prior to the termination of a clock pulse.

Claim 18

The apparatus of claim 13 wherein said means for generating a phase lead pulse comprises: first means for gating the reference signal with the negation of the clock signal, and means for enabling said first gating means only when the clock signal leads the reference signal, and wherein said means for generating a phase lag pulse comprises: second means for gating the clock signal with the negation of the reference signal, and means for enabling said second gating means only when the clock signal lags the reference signal.

Claim 19

The apparatus of claim 14 wherein said means for enabling said first gating means comprises: a pair of cross coupled NAND gates, wherein the first NAND gate receives the reference signal and the second NAND gate receives the negation of the clock signal, the output of said second NAND gate being applied to said first gating means; and said means for enabling said second gating means comprises: a pair of cross-coupled NAND gates, wherein the first NAND gate receives the clock signal and the second NAND gate receives the negation of the reference signal, the output of said second NAND gate being applied to said second gating means.

Claim 20

a phase locked loop clocking system for phase locking a clock signal with respect to a moving magnetic medium wherein said moving magnetic medium comprises at least two tracks, said first track containing spaced sets of flux reversals to and from a first magnetic state, and said second track containing spaced sets of flux reversals to and from a second magnetic state, said phase locked loop clocking system comprising; transducing means positioned in transducing relationship with said first and second tracks and responsive to said sets of flux reversals for producing pairs of first and second pulses of opposite signal polarity; means for generating a reference signal in response to the detected points; means for detecting a phase difference between said reference signal and said clocking signal; and means for controlling the frequency of said clocking signal so as to increase or decrease the frequency in response to a detected phase difference.

Claim 21

a phase locked loop clocking system for phase locking a clock signal with respect to a moving magnetic medium wherein said moving magnetic medium comprises at least two tracks, said first track containing spaced sets of flux reversals to and from a first magnetic state, and said second track containing spaced sets of flux reversals to and from a second magnetic state, said phase locked loop clocking system comprising; transducing means positioned in transducing relationship with said first and second tracks and responsive to said sets of flux reversals for producing pairs of first and second pulses of opposite signal polarity; means for generating a reference signal in response to the detected points; means for detecting a phase difference between said reference signal and said clocking signal; and means for controlling the frequency of said clocking signal so as to increase or decrease the frequency in response to a detected phase difference.

Claim 22

The apparatus of claim 16 wherein said means for detecting a point occurring between the peaks of said first and second pulses of opposite signal polarity comprises: positive threshold detection means for detecing when a pulse exceeds a positive threshold amplitude, said positive threshold detection means being operative to generate a threshold pulse during the time in which the amplitude of the pulse from said transducing means exceeds the positive threshold amplitude; and negative threshold detection means for detecting when a pulse exceeds a netative treshold amplitude, said negative threshold detection means being operative to generate a threshold pulse during the time in which the amplitude of the pulse from said transducing means exceeds the negative threshold amplitude.

Claim 23

The apparatus of claim 16 wherein said means for detecting a point occurring between the peaks of the first and second pulses further comprises: means for selecting the threshold pulse output from only one of the threshold detection means during the occurrence of any one pair of first and second pulses, and means for generating a train of selected threshold pulses wherein each selected threshold pulse defines a point occurring between the peaks of the first and second pulses.

Claim 24

The apparatus of claim 18 wherein the pairs of first and second pulses of opposite signal polarity from said transducing means comprise two types of pulse pairings, the first type of pulse pairing consisting of a first positively signed pulse followed by a second negatively signed pulse, the second type of pulse pairing consisting of a first negatively signed pulse followed by a second positively signed pulse, and said means for selecting the threshold pulse output from only one of the threshold detection means during the occurrence of any one pair of pulses comprises: first gating means for gating the threshold pulse output of the positive threshold detection means, means for enabling said first gating means during the occurrence of the second type of pulse pairing whereby the threshold pulse output from the positive threshold detection means is selected each time the second type of pulse pairing occurs, second gating means for gating the threshold pulse output of the negative threshold detection means, means for enabling said second gating means during the occurrence of the first type of paired pulses whereby the threshold pulse output from the positive threshold detection means is selected each time the second type of pulse pairing occurs.

Claim 25

The apparatus of claim 19 wherein said means for enabling said first gating means during the occurrence of the second type of pulse pairing comprises: means for gating the threshold pulse output from the negative threshold detection means during the occurrence of the second type of pulse pairing; and means for generating an enabling pulse in response to the gated threshold pulse output from the negative threshold detection means, and wherein said means for enabling said second gating means during the occurrence of the first type of pulse pairing comprises: means for gating the threshold pulse output from the positive threshold detection means during the occurrence of the first type of pulse pairing, and means for generating an enabling pulse in response to the gated threshold pulse output from the positive threshold detection means.

Claim 26

The apparatus of claim 20 wherein said means for generating a reference signal in response to the detected points comprises: means for generating a train of reference pulses wherein each reference pulse occurs in response to each selected threshold pulse in the train of selected threshold pulses from said means for generating a train of selected threshold pulses.

Claim 27

The apparatus of claim 21 wherein the train of reference pulses from said means for generating a train of reference pulses is applied to said means for detecting a phase difference between the clock signal and the reference signal, and wherein said means for detecting a phase difference comprises: means for generating a phase lead pulse in response to a clock pulse in the clock signal terminating prior to the termination of a reference pulse in the reference signal, and means for generating a phase lag pulse in response to a reference pulse iN the reference signal terminating prior to the termination of a clock pulse in the clock signal.

Claim 28

The apparatus of claim 22 wherein said means for generating a phase lead pulse comprises: first means for gating the reference signal with the negation of the clock signal, and means for enabling said first gating means only when the clock signal leads the reference signal, and wherein said means for generating a phase lag pulse comprises: second means for gating the clock signal with the negation of the reference signal, and means for enabling said second gating means when the clock signal lags the reference signal.