Combined sector pulse and data detection system

Claim 2

A sector identification and data detector system comprising: an input terminal adapted to receive an input signal train bearing sector identification and data signals, said sector signals having a frequency fS greater than the frequency fD of said data signals; frequency gating means coupled to said input terminal for generating a sector identification signal in response to the receipt thereof of signals lying in the range fS + or -Delta fs/2 where Delta fS is a predetermined permitted frequency deviation, said frequency gating means including: a first delay unit coupled to said input terminal for delaying said input signals by a first interval t1, and a first zero crossing detector coupled to said first delay unit for generating an output pulse in response to a change of polarity of the signals input thereto; first means for screening out input signals lying below the frequency fS - Delta fS/2, said first screening means including an AND gate having a first input coupled to the output of said zero crossing detector, and a first monstable multivibrator having a time-out interval t2, said multivibrator having an input coupled to said zero crossing detector and an output coupled to said AND gate for blocking transmission of signals therethrough during said time-out interval t2; second means for screening out input signals lying above the frequency fS + Delta fS/2; and means for terminating said sector identification signal when the frequency of said input signals lies outside said range; means coupled to said input terminal for decoding said data signals; phase lock loop means for clocking said decoding means; and means coupled to said frequency gating means for supplying a phase reference signal to said phase lock loop means.

Claim 3

A sector identification and data detector system comprising: an input terminal adapted to receive an input signal train bearing sector identification and data signals, said sector signals having a frequency fS greater than the frequency fD of said data signals; frequency gating means coupled to said input terminal for generating a sector identification signal in response to the receipt thereof of signals lying in the range fS + OR Delta fs/2 where Delta fS is a predetermined permitted frequency deviation, said frequency gating means including: a first delay unit coupled to said input terminal for delaying said input signals by a first interval t1, and a first zero crossing detector coupled to said first delay unit for generating an output pulse in response to a change of polarity of the signals input thereto; first means for screening out input signals lying below the frequency fS - Delta fS/2, said first screening means including an AND gate having a first input coupled to the output of said zero crossing detector, and a first monstable multivibrator having a time-out interval t2, said multivibrator having an input coupled to said zero crossing detector and an output coupled to said AND gate for blocking transmission of signals therethrough during said time-out interval t2; second means for screening out input signals lying above the frequency fS + Delta fS/2; and means for terminating said sector identification signal when the frequency of said input signals lies outside said range; means coupled to said input terminal for decoding said data signals; phase lock loop means for clocking said decoding means; and means coupled to said frequency gating means for supplying a phase reference signal to said phase lock loop means.

Claim 4

A sector identification and data detector system comprising: an input terminal adapted to receive an input signal train bearing sector identification and data signals, said sector signals having a frequency fS greater than the frequency fD of said data signals; frequency gating means coupled to said input terminal for generating a sector identification signal in response to the receipt thereof of signals lying in the range fS + OR Delta fs/2 where Delta fS is a predetermined permitted frequency deviation, said frequency gating means including: a first delay unit coupled to said input terminal for delaying said input signals by a first interval t1, and a first zero crossing detector coupled to said first delay unit for generating an output pulse in response to a change of polarity of the signals input thereto; first means for screening out input signals lying below the frequency fS - Delta fS/2, said first screening means including an AND gate having a first input coupled to the output of said zero crossing detector, and a first monstable multivibrator having a time-out interval t2, said multivibrator having an input coupled to said zero crossing detector and an output coupled to said AND gate for blocking transmission of signals therethrough during said time-out interval t2; second means for screening out input signals lying above the frequency fS + Delta fS/2; and means for terminating said sector identification signal when the frequency of said input signals lies outside said range; means coupled to said input terminal for decoding said data signals; phase lock loop means for clocking said decoding means; and means coupled to said frequency gating means for supplying a phase reference signal to said phase lock loop means.

Claim 5

The system of claim 1 wherein said second screening means includes a second monostable multivibrator having a time out interval t3, an input coupled to the output of said AND gate, and an output; a second zero crossing detector having an input coupled to said input terminal for generating a pulse in response to a change in polarity in said input signal train; an AND gate having an input coupled to said output of said second monostable multivibrator, a second input coupled to the output of said second zero crossing detector and an output; a first flip-flop having an input coupled to the output of said AND gate and an enabling output; and means coupled to said second monostable multivibrator for switching said first flip-flop to the opposite state to thereby terminate said enabling signal whenever the pulse output from said second zero crossing detector occurs later than said time out period t3 of said monostable multivibrator.

Claim 6

The system of claim 2 wherein said frequency gating means further includes an integrator coupled to said output of said second flip-flop and a level detector coupled to the output of said integrator for generating a second identification signal whenever the level of the input signal thereto rises above a predetermined threshold.

Claim 7

The system of claim 2 wherein said phase reference signal supplying means comprises a second delay unit having an input coupled to an output of said second monostable multivibrator and providing a delay t4, and a pulse generator having an input coupled to the output of said second delay unit for generating a pulse in response to receipt of a signal from said delay unit.

Claim 8

The system of claim 1 wherein said data decoding means comprises a polarity change sensor having a data input coupled to said input terminal and a clock input coupled to the output of said phase lock loop means.

Claim 9

The system of claim 4 wherein the delay intervals provided by said first delay unit, said second monostable multivibrator and said second delay unit are selected to provide a total signal delay T t1 + t3 + t4 t, where t is the expected data bit interval.

Claim 10

A sector identification and data detector system comprising: an input terminal adapted to receive input signals bearing sector and data signals, said sector signals having an expected frequency fS greater than the expected frequency fD of said data signals; a first delay unit having an input coupled to said input terminal and providing a first delay interval t1 for signals applied at the input thereto; a first zero crossing detector having an input coupled to the output of said first delay unit for generating an output pulse in response to a change in plurality of the signal input thereto; a first monostable multivibrator having a time out interval t2 and having an input coupled to the output of said first zero crossing detector; a first AND gate having a first input coupled to the output of said first zero crossing detector and a second input coupled to an output of said first monostable multivibrator; a second monostable vibrator having a time-out interval t3 and having an input coupled to the output of said first AND gate; a first flip-flop having an input coupled to an output of said second monostable multivibrator; a second AND gate having a first input coupled to an output of said first flip-flop and a second input coupled to the other output of said second monostable multivibrator; a second zero crossing detector having an input coupled to said input terminal for generating an output pulse whenever the signal input thereto changes polarity, a third AND gate having a first input coupled to the first output of said second monostable multivibrator and a second input coupled to the output of said second zero crossing detector; a second flip-flop having a first input coupled to the output of said third AND gate and a second input coupled to the output of said second AND gate; an integrator having an input coupled to the output of said second flip-flop; a level detector having an input coupled to the output of said integrator; a phase lock loop having first and second phase reference inputs and a voltage controlled oscillator for generating clocking signals, said first phase reference input being coupled to the output of said voltage controlled oscillator; a polarity change sensor having a data input coupled to said input terminal and a clock input coupled to the output of said voltage controlled oscillator; and means having an input coupled to said first output of said second monostable multivibrator for generating a second phase reference signal, said last-named means having an output coupled to said second phase reference input of said phase lock loop.

Claim 11

A sector identification and data detector system comprising: an input terminal adapted to receive input signals bearing sector and data signals, said sector signals having an expected frequency fS greater than the expected frequency fD of said data signals; a first delay unit having an input coupled to said input terminal and providing a first delay interval t1 for signals applied at the input thereto; a first zero crossing detector having an input coupled to the output of said first delay unit for generating an output pulse in response to a change in plurality of the signal input thereto; a first monostable multivibrator having a time out interval t2 and having an input coupled to the output of said first zero crossing detector; a first AND gate having a first input coupled to the output of said first zero crossing detector and a second input coupled to an output of said first monostable multivibrator; a second monostable vibrator having a time-out interval t3 and having an input coupled to the output of said first AND gate; a first flip-flop having an input coupled to an output of said second monostable multivibrator; a second AND gate having a first input coupled to an output of said first flip-flop and a second input coupled to the other output of said second monostable multivibrator; a second zero crossing detector having an input coupled to said input terminal for generating an output pulse whenever the signal input thereto changes polarity, a third AND gate having a first input coupled to the first output of said second monostable multivibrator and a second input coupled to the output of said second zero crossing detector; a second flip-flop having a first input coupled to the output of said third AND gate and a second input coupled to the output of said second AND gate; an integrator having an input coupled to the output of said second flip-flop; a level detector having an input coupled to the output of said integrator; a phase lock loop having first and second phase reference inputs and a voltage controlled oscillator for generating clocking signals, said first phase reference input being coupled to the output of said voltage controlled oscillator; a polarity change sensor having a data input coupled to said input terminal and a clock input coupled to the output of said voltage controlled oscillator; and means having an input coupled to said first output of said second monostable multivibrator for generating a second phase reference signal, said last-named means having an output coupled to said second phase reference input of said phase lock loop.