Fabrication technique for high density integrated circuits

Claim 1

A method for making an integrated circuit comprising the steps of: forming a first layer of relatively lightly doped semiconductor material of a first conductivity type on an insulating substrate; removing portions of said first layer to provide a plurality of spaced elongated regions, each of said elongated regions being isolated, each of said elongated regions having a plurality of spaced openings therein exposing said insulating substrate; forming a composite dielectric layer on said elongated regions; removing portions of said composite dielectric layer, thereby forming a plurality of gate dielectric regions on said elongated regions, each of said gate dielectric regions extending, respectively, between a pair of said spaced openings, leaving exposed first and second elongated sections of each of said elongated regions; passing impurities into and heavily doping said exposed first and second elongated sections, said composite dielectric layer acting to mask said passing of said impurities; forming a first insulator on said exposed first and second elongated sections; forming a conductive layer on an entire upper surface of said integrated circuit; and removing portions of said conductive layer to form a plurality of spaced conductors, each of said spaced conductors acting as gate electrodes on at least one of said gate dielectric regions.

Claim 2

A method for making an integrated circuit comprising the steps of: forming a first layer of relatively lightly doped semiconductor material of a first conductivity type on an insulating substrate; removing portions of said first layer to provide a plurality of spaced elongated regions, each of said elongated regions being isolated, each of said elongated regions having a plurality of spaced openings therein exposing said insulating substrate; forming a composite dielectric layer on said elongated regions; removing portions of said composite dielectric layer, thereby forming a plurality of gate dielectric regions on said elongated regions, each of said gate dielectric regions extending, respectively, between a pair of said spaced openings, leaving exposed first and second elongated sections of each of said elongated regions; passing impurities into and heavily doping said exposed first and second elongated sections, said composite dielectric layer acting to mask said passing of said impurities; forming a first insulator on said exposed first and second elongated sections; forming a conductive layer on an entire upper surface of said integrated circuit; and removing portions of said conductive layer to form a plurality of spaced conductors, each of said spaced conductors acting as gate electrodes on at least one of said gate dielectric regions.

Claim 8

A method for fabricating an MNOS memory matrix comprising the steps of: epitaxially forming a first silicon layer on an insulating substrate, said first silicon layer being single crystal, of a first conductivity type, and being relatively lightly doped; selectively removing portions of said first silicon layer to provide a plurality of spaced, isolated elongated silicon regions arranged in columns on said insulating substrate, each of said elongated silicon regions having a plurality of openings therein, said openings being spaced and exposing said insulating substrate, said openings forming substantially horizontally aligned rows; forming a composite dielectric layer on said elongated silicon region, said composite dielectric including a relatively thin silicon dioxide layer on said elongated silicon regions and a silicon nitride layer on said silicon dioxide layer; selectively removing portions of said composite dielectric layer to provide a plurality of essentially rectangular dielectric regions on said elongated silicon columns, said rectangular dielectric regions being spaced and extending, respectively, between each of said openings, leaving exposed first and second elongated sections of each of said elongated silicon regions; diffusing impurities of a second conductivity type into said exposed first and second elongated sections, said exposed first and second elongated sections to be heavily doped; thermally growing a silicon dioxide layer on said exposed first and second elongated sections; forming a patterned metal layer on the upper surface of said MNOS memory matrix, said patterned metal layer forming a plurality of substantially horizontal parallel conductors, each acting as a gate electrode for one of said substantially horizontally aligned rows of openings.

Claim 9

A method for fabricating an MNOS memory matrix comprising the steps of: epitaxially forming a first silicon layer on an insulating substrate, said first silicon layer being single crystal, of a first conductivity type, and being relatively lightly doped; selectively removing portions of said first silicon layer to provide a plurality of spaced, isolated elongated silicon regions arranged in columns on said insulating substrate, each of said elongated silicon regions having a plurality of openings therein, said openings being spaced and exposing said insulating substrate, said openings forming substantially horizontally aligned rows; forming a composite dielectric layer on said elongated silicon region, said composite dielectric including a relatively thin silicon dioxide layer on said elongated silicon regions and a silicon nitride layer on said silicon dioxide layer; selectively removing portions of said composite dielectric layer to provide a plurality of essentially rectangular dielectric regions on said elongated silicon columns, said rectangular dielectric regions being spaced and extending, respectively, between each of said openings, leaving exposed first and second elongated sections of each of said elongated silicon regions; diffusing impurities of a second conductivity type into said exposed first and second elongated sections, said exposed first and second elongated sections to be heavily doped; thermally growing a silicon dioxide layer on said exposed first and second elongated sections; forming a patterned metal layer on the upper surface of said MNOS memory matrix, said patterned metal layer forming a plurality of substantially horizontal parallel conductors, each acting as a gate electrode for one of said substantially horizontally aligned rows of openings.