Noise generator

Claim 1

A noise generator more particularly for the conversion of a digital signal into a stochastic representation comprising a binary coded decimal counter including as many stages in series producing the values from 0 to 9 in binary form as there are decades of the noise to be produced, input means for applying clock pulses to the stage of the counter whose weighting is the heaviest and in which each of the other stages receives, from the preceding stage, corresponding to the decade whose weighting is immediately greater, a signal whose frequency is ten times smaller than the frequency of the signal received by that preceding stage, each stage of said counter including gating means for producing successive values in the order: 5, 2, 7, 1, 8, 3, 6, 0, 9, 4 to appear at the outputs thereof, wherein each stage of said counter includes first, second, third, and fourth J-K flip-flops, said gating means including a first NAND gate having one input connected to the reset output of said first flip-flop, and a second input connected to the reset output of said second flip-flop, a second NAND gate having one input connected to the output of said first NAND gate and a second input connected to the set output of said third flip-flop, the output of said second NAND gate being connected to the J input of said first flip-flop, a third NAND gate having one input connected to the set output of said first flip-flop and a second input connected to the reset output of said second flip-flop, and a fourth NAND gate having one input connected to the output of said third NAND gate and a second input connected to the set output of said third flip-flop, the output of said fourth NAND gate being connected to the K input of said first flip-flop.