Random error correcting system

Claim 2

An error correcting system having an encoder for generating parity bits from information bits applied thereto and applying said information bits and said parity bits to utilization means, said encoder including in combination: sample and storage means having six stages for receiving and storing six successive information bits; means for generating parity bits connected to said sample and storage means, said parity bit generating means including modulo 2 adder means for generating each parity bit by taking the modulo 2 sum of a predetermined one of said information bits, the two information bits immediately precedEnt thereto and the information bit five bits precedent to said predetermined information bit to thereby provide a parity bit associated with said predetermined information bit; and switch means for alternately applying said information bits and the parity bits associated therewith to said utilization means.

Claim 3

An error correcting system as recited in claim 1 further including a decoder comprising: means for receiving said information bits and said parity bits; second sample and storage means having six stages for storing six of said received information bits connected to said receiving means; means coupled to said receiving means and to said second sample and storage means for generating syndrome bits, said syndrome bit generating means including second modulo 2 adder means for generating each syndrome bit by taking the modulo 2 sum of a predetermined one of said received information bits, the two information bits immediately precedent thereto, the information bit five bits precedent to said predetermined information bit and the parity bit associated with said predetermined information bit to thereby generate a syndrome bit associated with said predetermined information bit; third sample and storage means having six stages for storing six syndrome bits connected to said syndrome bit generating means; third modulo 2 adder means connected to said third sample and storage means for providing bits representative of the modulo 2 sum of the syndrome bit associated with said predetermined information bit and the syndrome bit immediately precedent thereto; fourth modulo 2 adder means connected to said third sample and storage means for providing bits representative of the modulo 2 sum of the two syndrome bits immediately preceding the two syndrome bits applied to said third modulo 2 adder means; counting means connected to said third sample and storage means and to said third and fourth modulo 2 adder means for taking the sum of the two syndrome bits immediately preceding the two syndrome bits applied to said fourth modulo 2 adder means and the bits provided by said third and fourth modulo 2 adder means, said counting means including means for providing a correction signal when said last mentioned sum exceeds two; and correction means responsive to said correction signal for reversing the polarity of the information bit five bits precedent to said predetermined received information bit in response to said correction signal.

Claim 4

An error correcting system as recited in claim 2 wherein said encoder and decoder each includes clock means coupled to each of said sample and storage means for sequentially shifting bits between respective stages thereof.

Claim 5

An error correcting system as recited in claim 3 wherein each of said sample and storage means includes a shift register having six stages.

Claim 6

An encoder for generating parity bits from information bits applied thereto usable in an error correction system, said encoder comprising: sample and storage means having six stages including an input stage for serially receiving and storing said information bits, said stages being designated as first through sixth stages starting with said input stage; means for applying each information bit to said first stage of said sample and storage means for storage therein; means for sequentially shifting each information bit from said first stage to said second through sixth stages; a modulo 2 adder having inputs and an output, said inputs being connected to the first, second, third and sixth stages of said sample and storage means; switch means having two input terminals and an output terminal, one of said input terminals being coupled to the first stage of said sample and storage means and the other terminal being connected to the output of said modulo 2 adder; and means connected to said switch means for causing said switch means to alternately cOuple said first stage and said output terminal of said modulo 2 adder to said output terminal.

Claim 7

An encoder for generating parity bits from information bits applied thereto usable in an error correction system, said encoder comprising: sample and storage means having six stages including an input stage for serially receiving and storing said information bits, said stages being designated as first through sixth stages starting with said input stage; means for applying each information bit to said first stage of said sample and storage means for storage therein; means for sequentially shifting each information bit from said first stage to said second through sixth stages; a modulo 2 adder having inputs and an output, said inputs being connected to the first, second, third and sixth stages of said sample and storage means; switch means having two input terminals and an output terminal, one of said input terminals being coupled to the first stage of said sample and storage means and the other terminal being connected to the output of said modulo 2 adder; and means connected to said switch means for causing said switch means to alternately cOuple said first stage and said output terminal of said modulo 2 adder to said output terminal.

Claim 8

An encoder as recited in claim 5 wherein said sample and storage means includes a six stage shift register.

Claim 9

A decoder for extracting and correcting information bits from a bit stream including information and parity bits, said decoder comprising: means for serially receiving said information bits; means connected to said information bit receiving means for generating syndrome bits, each syndrome bit being generated by taking the modulo 2 sum of a predetermined one of said parity bits, a predetermined one of said received information bits, the two information bits immediately preceding said one of said received information bits and the information bits five bits precedent said predetermined one of said received information bits; means for serially receiving said syndrome bits connected to said syndrome bit generating means; first combining means connected to said syndrome bit receiving means for generating bits representative of the modulo 2 sum of a first predetermined pair of adjacent syndrome bits; second combining means connected to said syndrome bit receiving means for generating bits representative of the modulo 2 sum of a second predetermined pair of adjacent syndrome bits immediately preceding said first predetermined pair of adjacent syndrome bits; counting means connected to said syndrome bit receiving means and said first and second combining means, said counting means being responsive to a third predetermined pair of adjacent syndrome bits immediately preceding said second predetermined pair of adjacent syndrome bits and the modulo 2 sum representative bits from each of said first and second combining means for generating a correction bit when the sum of said third predetermined pair of adjacent syndrome bits and said modulo 2 sum representative bits exceeds two; and correcting means connected to said information bit receiving means and said counting means for correcting one of said received information bits in response to said correction bit.

Claim 10

A decoder for extracting and correcting information bits from a bit stream including information and parity bits, said decoder comprising: means for serially receiving said information bits; means connected to said information bit receiving means for generating syndrome bits, each syndrome bit being generated by taking the modulo 2 sum of a predetermined one of said parity bits, a predetermined one of said received information bits, the two information bits immediately preceding said one of said received information bits and the information bits five bits precedent said predetermined one of said received information bits; means for serially receiving said syndrome bits connected to said syndrome bit generating means; first combining means connected to said syndrome bit receiving means for generating bits representative of the modulo 2 sum of a first predetermined pair of adjacent syndrome bits; second combining means connected to said syndrome bit receiving means for generating bits representative of the modulo 2 sum of a second predetermined pair of adjacent syndrome bits immediately preceding said first predetermined pair of adjacent syndrome bits; counting means connected to said syndrome bit receiving means and said first and second combining means, said counting means being responsive to a third predetermined pair of adjacent syndrome bits immediately preceding said second predetermined pair of adjacent syndrome bits and the modulo 2 sum representative bits from each of said first and second combining means for generating a correction bit when the sum of said third predetermined pair of adjacent syndrome bits and said modulo 2 sum representative bits exceeds two; and correcting means connected to said information bit receiving means and said counting means for correcting one of said received information bits in response to said correction bit.

Claim 11

A decoder as recited in claim 7 wherein said counting means is further coupled to said syndrome bit receiving means and includes means for correcting predetermined ones of said syndrome bits in response to said correction signal.

Claim 12

A decoder as recited in claim 8 wherein each of said information bit receiving means and said syndrome bit receiving means includes a six stage shift register having an input stage, said stages being designated as first through sixth stages starting with said input stage, said syndrome bit generating means being connected to the first, second, third and sixth stages of the shift register included in said information bit receiving means, the sixth stage thereof also being connected to said correcting means; said first combining means being connected to the first and second stages of the shift register included in said syndrome bit receiving means, said second combining means being connected to the third and fourth stages thereof, and said counting means being connected to the fifth and sixth stages thereof.

Claim 13

A decoder as recited in claim 9 wherein said counting means has syndrome bit correcting output means, said output means being connected to said first, fourth and fifth stages of the shift register included in said syndrome bit receiving means.

Claim 14

A decoder for extracting and correcting information bits from a bit stream including information and parity bits, said decoder comprising: first sample and storage means having six stages including an input stage for serially receiving and storing said information bits, said stages being designated as first through sixth stages starting with said input stage; first modulo 2 adder means coupled to the first, second, third and sixth stages of said first sample and storage means; means coupled to said sample and storage means and to said modulo 2 adder means for applying said information bits to said sample and storage means and said parity bits to said modulo 2 adder means, respectively, said first modulo 2 adder means being responsive to said parity bits and the information bits stored in the first, second, third and sixth stages of said first sample and storage means for generating syndrome bits, each syndrome bit representative of the modulo 2 sum of said last mentioned information bits and one of said parity bits; second sample and storage means connected to said first modulo 2 adder means for serially receiving and storing said syndrome bits, said second sample and storage means having six stages including an input stage, said stages being designated as first through sixth stages starting with said input stage; second modulo 2 adder means coupled to the first and second stages of said second sample and storage means for taking the modulo 2 sum of the contents thereof and providing a signal representative of said sum; third modulo 2 adder means coupled to the third and fourth stages of said second sample and storage means for taking the modulo 2 sum of the contents thereof and providing a signal representative of said sum; counting means having inputs coupled to said second and third modulo 2 adders and to the fifth and sixth stages of said second sample and storage means for receiving bits therefrom, said counting means being responsive to the sum of the bits applied thereto to provide a correction signal when said sum exceeds two; and fourth modulo 2 adder means coupled to the sixth stage of said first sample and storage means and to said counting means, said third modulo 2 adder means being responsive to the modulo 2 sum of the contents of said sixth stage of said first sample and storage means and to said correction signal to provide a corrected information signal.

Claim 15

A decoder for extracting and correcting information bits from a bit stream including information and parity bits, said decoder comprising: first sample and storage means having six stages including an input stage for serially receiving and storing said information bits, said stages being designated as first through sixth stages starting with said input stage; first modulo 2 adder means coupled to the first, second, third and sixth stages of said first sample and storage means; means coupled to said sample and storage means and to said modulo 2 adder means for applying said information bits to said sample and storage means and said parity bits to said modulo 2 adder means, respectively, said first modulo 2 adder means being responsive to said parity bits and the information bits stored in the first, second, third and sixth stages of said first sample and storage means for generating syndrome bits, each syndrome bit representative of the modulo 2 sum of said last mentioned information bits and one of said parity bits; second sample and storage means connected to said first modulo 2 adder means for serially receiving and storing said syndrome bits, said second sample and storage means having six stages including an input stage, said stages being designated as first through sixth stages starting with said input stage; second modulo 2 adder means coupled to the first and second stages of said second sample and storage means for taking the modulo 2 sum of the contents thereof and providing a signal representative of said sum; third modulo 2 adder means coupled to the third and fourth stages of said second sample and storage means for taking the modulo 2 sum of the contents thereof and providing a signal representative of said sum; counting means having inputs coupled to said second and third modulo 2 adders and to the fifth and sixth stages of said second sample and storage means for receiving bits therefrom, said counting means being responsive to the sum of the bits applied thereto to provide a correction signal when said sum exceeds two; and fourth modulo 2 adder means coupled to the sixth stage of said first sample and storage means and to said counting means, said third modulo 2 adder means being responsive to the modulo 2 sum of the contents of said sixth stage of said first sample and storage means and to said correction signal to provide a corrected information signal.

Claim 16

A decoder as recited in claim 11 wherein said counting means has an output coupled to the first, fourth and fifth stages of the second sample and storage means, said second sample and storage means being responsive to said counting means to change the polarity of the bits stored in said first, fourth and fifth stages when the sum of the bits applied to said counting means exceeds two.

Claim 17

A decoder as recited in claim 12 further including clock means coupled to said first and second sample and storage means for sequentially shifting said information and syndrome bits from the first through sixth stages of said first and second sample and storage means, respectively.

Claim 18

A decoder as recited in claim 13 wherein each of said first and second sample and storage means includes a shift register having six stages designated as first through sixth stages, each stage of each shift register being connected to the correspondingly designated stage of one of said first and second sample and storage means.