US3873820A
Expired / Lapsed
US
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Apparatus for checking partial products in iterative multiply operations
Assignee: International Business Machines Corp
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Filing: 1974-01-31
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Granted: 1975-03-25
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Expires: 1994-01-31
Abstract
Abstract Apparatus for detecting multiplication errors in digital computers where multiplication is executed by iterative addition. A predicted residue is generated for each iteration by modifying the residue of the previous partial product according to the multiplier bits in the current iteration and the multiplicand residue. The current partial product is obtained and its residue generated. The generated current partial product residue is compared to the predicted residue for the current iteration to determine whether a hardware error has occurred. The process is repeated for each iteration, thereby eliminating the possibility of offsetting errors.
Inventors
- 👤 Joseph Ward Parr
- 👤 Kwang Yue Sih
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 04:18
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/104
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
197 words
Apparatus for detecting hardware errors in an iterative addition multiply unit of a digital computer wherein the operands for the multiply unit are determined by decoding a plurality of multiplier bits during each iteration coMprising: residue prediction means operating concurrently with said multiply unit including (a) residue generating means having a first input connected to said multiply unit for receiving the multiplicand bits therefrom and a second input connected to said multiply unit for receiving the decoded multiplier bits for the current iteration therefrom, said residue generating means operating on said multiplicand bits and decoded multiplier bits to generate current multiple residues, and (b) accumulator means connected to said residue generating means for combining said current multiple residues with the predicted residue for the previous iteration to yield the current predicted residue; residue generator means connected to the output of said multiply unit for determining the actual residue of the partial product generated by the multiply unit for the current iteration; and comparator means connected to said residue prediction means and said residue generator means for comparing the predicted residue with the actual residue and producing an error signal when the result of the compare is unequal.
Claim 2
Dependent Claim
197 words
Apparatus for detecting hardware errors in an iterative addition multiply unit of a digital computer wherein the operands for the multiply unit are determined by decoding a plurality of multiplier bits during each iteration coMprising: residue prediction means operating concurrently with said multiply unit including (a) residue generating means having a first input connected to said multiply unit for receiving the multiplicand bits therefrom and a second input connected to said multiply unit for receiving the decoded multiplier bits for the current iteration therefrom, said residue generating means operating on said multiplicand bits and decoded multiplier bits to generate current multiple residues, and (b) accumulator means connected to said residue generating means for combining said current multiple residues with the predicted residue for the previous iteration to yield the current predicted residue; residue generator means connected to the output of said multiply unit for determining the actual residue of the partial product generated by the multiply unit for the current iteration; and comparator means connected to said residue prediction means and said residue generator means for comparing the predicted residue with the actual residue and producing an error signal when the result of the compare is unequal.
Claim 3
Dependent Claim
59 words
Apparatus according to claim 1 wherein said residue generating means further comprising: a first residue generator means connected to said first input for determining the residue of the multiplicand; and a second residue generator means connected to said second input and to said first residue generator means for determining the residues of the current multiplies to the multiply unit.
Claim 4
Dependent Claim
66 words
The apparatus according to claim 2 wherein said second residue generator means comprises: residue adjust means for adjusting the residue of the multiplicand to convert it to positive, and operand residue generating means connected to said residue adjust means for generating the residues of the current multiples to the multiply unit based on the adjust multiplicand residue and the decoded multiplier bits for the current iteration.
Claim 5
Dependent Claim
38 words
The apparatus according to claim 3 wherein said residue prediction means further comprises a buffer means connected to said accumulator means and said comparator means for delaying the current predicted residue until the current actual residue is produced.
Claim 6
Dependent Claim
228 words
Apparatus for detecting hardware errors in an iterative addition multiply unit of a digital computer wherein the multiples for the multiply unit are determined by decoding a plurality of multiplier bits during each iteration comprising: residue prediction means operating concurrently with said multiply unit for generating a predicted residue for partial product obtained during the current iteration, said residue prediction means including a first residue generating means connected to said multiply unit for determining the residue of the multiplicand, a second residue generating means connected to said multiply unit and to said first residue generating means for determining the residue of the current multiples to the multiply unit based on the multiplicand residue and the decoded multiplier bits, accumulator means connected to said second residue generating means for combining the current operand residues with the predicted residue for the previous iteration to yield the current predicted residue, and buffer means connected to the accumulator means for delaying said current predicted residue until the actual residue is produced; residue generator means connected to the output of said multiply unit for determining the actual residue of the partial product generated by the multiply unit; and comparator means connected to said residue prediction means and said residue generator means for comparing the predicted residue with the actual residue and producing an error signal when the result of the compare is unequal.
Claim 7
Dependent Claim
228 words
Apparatus for detecting hardware errors in an iterative addition multiply unit of a digital computer wherein the multiples for the multiply unit are determined by decoding a plurality of multiplier bits during each iteration comprising: residue prediction means operating concurrently with said multiply unit for generating a predicted residue for partial product obtained during the current iteration, said residue prediction means including a first residue generating means connected to said multiply unit for determining the residue of the multiplicand, a second residue generating means connected to said multiply unit and to said first residue generating means for determining the residue of the current multiples to the multiply unit based on the multiplicand residue and the decoded multiplier bits, accumulator means connected to said second residue generating means for combining the current operand residues with the predicted residue for the previous iteration to yield the current predicted residue, and buffer means connected to the accumulator means for delaying said current predicted residue until the actual residue is produced; residue generator means connected to the output of said multiply unit for determining the actual residue of the partial product generated by the multiply unit; and comparator means connected to said residue prediction means and said residue generator means for comparing the predicted residue with the actual residue and producing an error signal when the result of the compare is unequal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-24 | 1978-09-23 | 1979-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-24 | 1982-09-23 | 1983-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-24 | 1986-09-23 | 1987-03-25 | $7700.00 | Window Closed / Lapsed |