Signal processing system

Claim 2

A signal processing system for performing signal compression and/Or expansion with respect to analog information signals which are being reproduced at a rate other than that at which said signals have been recorded comprising: a. delay line means for receiving said reproduced analog information signals and for propagating said analog information signals with controllable time transformation; b. means for controlling said delay line means to produce said time transformation; and c. means for compensating for a DC level-deviation of an output signal read out from said delay line means.

Claim 3

A signal processing system according to claim 1, in which said delay line means comprise a pair of shift registers which are used alternately for writing in and reading out said analog information signals.

Claim 4

A signal processing system according to claim 2, in which said delay line means further comprises means for recirculating the signal read out from each said shift register to an input thereof.

Claim 5

A signal processing system according to claim 2, in which said control means is provided with a first clock signal generator the frequency of which is set in relation to the rate at which said information signal is reproduced and a second clock signal generator of fixed frequency.

Claim 6

A signal processing system according to claim 4, in which an information signal is alternately written in one of said registers by said first clock signal while a second information signal is read out from the other of said registers by said second clock signal.

Claim 7

A signal processing system for performing signal compression and/or expansion with respect to analog information signals which are being reproduced at a rate other than that at which said signals have been recorded, comprising: delay line means for receiving the reproduced analog information signals and for propagating said analog information signals with controllable time transformation; means for controlling said delay line means to determine said time transformation of the signals propagated therealong; and means for compensating a DC level-diviation of an output signal read out from said delay line means including a. means for receiving said reproduced information signals and for converting them into a pair of input signals differing in phase by 180* from each other; b. means for alternately sampling said pair of oppositely phased input signals and for supplying a sampled signal to said delay line means; c. means for detecting an in phase component of said output signal read out from said delay line means and for producing a pair of output signals differing in phase from each other; and d. means for differentially processing said pair of output signals derived from said detecting means.

Claim 8

A signal processing system for performing signal compression and/or expansion with respect to analog information signals which are being reproduced at a rate other than that at which said signals have been recorded, comprising: delay line means for receiving the reproduced analog information signals and for propagating said analog information signals with controllable time transformation; means for controlling said delay line means to determine said time transformation of the signals propagated therealong; and means for compensating a DC level-diviation of an output signal read out from said delay line means including a. means for receiving said reproduced information signals and for converting them into a pair of input signals differing in phase by 180* from each other; b. means for alternately sampling said pair of oppositely phased input signals and for supplying a sampled signal to said delay line means; c. means for detecting an in phase component of said output signal read out from said delay line means and for producing a pair of output signals differing in phase from each other; and d. means for differentially processing said pair of output signals derived from said detecting means.

Claim 9

A signal processing system according to claim 6, in which said differential processing means comprises a differential amplifier having a pair of output terminals from which said pair of input signals are derived respectively.

Claim 10

A signal processing system according to claim 6, in which said detecting means comprises two signal holding circuits, respectively driven by clock signals differing in phase by 180* from each other, for holding said read-out signal from said delay line means for at least twice the duration of said sampled signal.

Claim 11

A signal processing system according to claim 6, in which said differential processing means includes a differential amplifier having a pair of input terminals to which said pair of output signals are separately supplied.

Claim 12

A signal processing system according to claim 1, in which said D.C. level compensating means comprises inverter means interposed in said delay line means for inverting said information signal in the course of the propagation of the latter along said delay line means.

Claim 13

A signal processing system for sound signal compression and/or expansion comprising: a. a first differential amplifier having an input terminal and a pair of output terminals, said input terminAl being coupled to an external source of an information signal so as to produce a pair of information signals reversed in phase with respect to each other from said output terminals; b. switching means coupled to said output terminals for alternately sampling said oppositely phased information signals; c. a shift register connected with said switching means for propagating said signals sampled by said switching means with time transformation; d. a clock signal generator for controlling said switching means and said shift register to produce said time transformation in signals read out of said shift register; e. a pair of signal holding circuits for holding the in phase components of said signals read out of said shift register; and f. a second differential amplifier having a pair of input terminals and an output terminal, said input terminals respectively being coupled to said pair of signal holding circuits and said output terminal being coupled to a system output.

Claim 14

A signal processing system for sound signal compression and/or expansion comprising: a. a first differential amplifier having an input terminal and a pair of output terminals, said input terminAl being coupled to an external source of an information signal so as to produce a pair of information signals reversed in phase with respect to each other from said output terminals; b. switching means coupled to said output terminals for alternately sampling said oppositely phased information signals; c. a shift register connected with said switching means for propagating said signals sampled by said switching means with time transformation; d. a clock signal generator for controlling said switching means and said shift register to produce said time transformation in signals read out of said shift register; e. a pair of signal holding circuits for holding the in phase components of said signals read out of said shift register; and f. a second differential amplifier having a pair of input terminals and an output terminal, said input terminals respectively being coupled to said pair of signal holding circuits and said output terminal being coupled to a system output.

Claim 15

A signal processing system for signal compression and/or expansion of reproduced information signals comprising: a. a plurality of shift registers arranged in two groups, one of said groups of registers being alternately used for writing in a reproduced information signal and for reading out said information signal previously written therein, and the other of said groups of registers being alternately used for writing in a reproduced information signal and for reading out said information signal previously written in said other group while said one group is being used for reading out and writing, respectively; b. means for generating a first clock signal having a frequency corresponding to the rate at which said information signal is reproduced, said first clock signal being used for writing said information signal in said one and other groups of shift registers; c. means for generating a second clock signal having a fixed frequency, said second clock signal being used for reading out said information signal from said one and other groups of shift registers; and d. inverting means interposed between said shift registers in each of said groups for inverting the phase of said information signal written in the respective group of shift registers prior to the reading out thereof.

Claim 16

A signal processing system for signal compression and/or expansion of reproduced information signals comprising: a. a plurality of shift registers arranged in two groups, one of said groups of registers being alternately used for writing in a reproduced information signal and for reading out said information signal previously written therein, and the other of said groups of registers being alternately used for writing in a reproduced information signal and for reading out said information signal previously written in said other group while said one group is being used for reading out and writing, respectively; b. means for generating a first clock signal having a frequency corresponding to the rate at which said information signal is reproduced, said first clock signal being used for writing said information signal in said one and other groups of shift registers; c. means for generating a second clock signal having a fixed frequency, said second clock signal being used for reading out said information signal from said one and other groups of shift registers; and d. inverting means interposed between said shift registers in each of said groups for inverting the phase of said information signal written in the respective group of shift registers prior to the reading out thereof.