US3870997A — Automatic gain integrator control

Claim 1

Independent Claim 248 words

In a radar counter-countermeasure system, including the combination of a normal radar system and counter-countermeasure circuitry, a radar receiver comprising: a. an IF amplifier whose signal input is received from the pre IF stage of a normal radar system, b. an IF limiter to which the output of said IF amplifier is fed, c. a video detector connected to the output of said IF limiter, d. the video signal output of said detector being fed to counter-countermeasure circuitry and operator range scope of said normal radar system, e. a memory and delayed AGC circuit means whose output is connected to and controls the gain of said IF amplifier for maintaining the target IF signal at desired operating threshold level, f. radar video, AGC, and gate signals from the normal radar system being fed to said memory and delayed AGC circuit at respective inputs thereto, g. said memory and delayed AGC circuit also being connected to the counter-countermeasure circuitry for receiving control signals therefrom, h. said memory and delayed AGC circuit providing delayed AGC voltage during normal target tracking, and providing AGC memory during periods of interference by storing the last gain setting and coasting at that setting upon receiving said control signals from the counter-countermeasure circuitry, wherein target video signal level suppression resulting from intentional and unintentional interferences is prevented and target video signal level at the output of said detector is controlled only by AGC action caused by the target itself even in the presence of interference.

Claim 2

Dependent Claim 248 words

In a radar counter-countermeasure system, including the combination of a normal radar system and counter-countermeasure circuitry, a radar receiver comprising: a. an IF amplifier whose signal input is received from the pre IF stage of a normal radar system, b. an IF limiter to which the output of said IF amplifier is fed, c. a video detector connected to the output of said IF limiter, d. the video signal output of said detector being fed to counter-countermeasure circuitry and operator range scope of said normal radar system, e. a memory and delayed AGC circuit means whose output is connected to and controls the gain of said IF amplifier for maintaining the target IF signal at desired operating threshold level, f. radar video, AGC, and gate signals from the normal radar system being fed to said memory and delayed AGC circuit at respective inputs thereto, g. said memory and delayed AGC circuit also being connected to the counter-countermeasure circuitry for receiving control signals therefrom, h. said memory and delayed AGC circuit providing delayed AGC voltage during normal target tracking, and providing AGC memory during periods of interference by storing the last gain setting and coasting at that setting upon receiving said control signals from the counter-countermeasure circuitry, wherein target video signal level suppression resulting from intentional and unintentional interferences is prevented and target video signal level at the output of said detector is controlled only by AGC action caused by the target itself even in the presence of interference.

Claim 3

Dependent Claim 248 words

In a radar counter-countermeasure system, including the combination of a normal radar system and counter-countermeasure circuitry, a radar receiver comprising: a. an IF amplifier whose signal input is received from the pre IF stage of a normal radar system, b. an IF limiter to which the output of said IF amplifier is fed, c. a video detector connected to the output of said IF limiter, d. the video signal output of said detector being fed to counter-countermeasure circuitry and operator range scope of said normal radar system, e. a memory and delayed AGC circuit means whose output is connected to and controls the gain of said IF amplifier for maintaining the target IF signal at desired operating threshold level, f. radar video, AGC, and gate signals from the normal radar system being fed to said memory and delayed AGC circuit at respective inputs thereto, g. said memory and delayed AGC circuit also being connected to the counter-countermeasure circuitry for receiving control signals therefrom, h. said memory and delayed AGC circuit providing delayed AGC voltage during normal target tracking, and providing AGC memory during periods of interference by storing the last gain setting and coasting at that setting upon receiving said control signals from the counter-countermeasure circuitry, wherein target video signal level suppression resulting from intentional and unintentional interferences is prevented and target video signal level at the output of said detector is controlled only by AGC action caused by the target itself even in the presence of interference.

Claim 4

Dependent Claim 248 words

In a radar counter-countermeasure system, including the combination of a normal radar system and counter-countermeasure circuitry, a radar receiver comprising: a. an IF amplifier whose signal input is received from the pre IF stage of a normal radar system, b. an IF limiter to which the output of said IF amplifier is fed, c. a video detector connected to the output of said IF limiter, d. the video signal output of said detector being fed to counter-countermeasure circuitry and operator range scope of said normal radar system, e. a memory and delayed AGC circuit means whose output is connected to and controls the gain of said IF amplifier for maintaining the target IF signal at desired operating threshold level, f. radar video, AGC, and gate signals from the normal radar system being fed to said memory and delayed AGC circuit at respective inputs thereto, g. said memory and delayed AGC circuit also being connected to the counter-countermeasure circuitry for receiving control signals therefrom, h. said memory and delayed AGC circuit providing delayed AGC voltage during normal target tracking, and providing AGC memory during periods of interference by storing the last gain setting and coasting at that setting upon receiving said control signals from the counter-countermeasure circuitry, wherein target video signal level suppression resulting from intentional and unintentional interferences is prevented and target video signal level at the output of said detector is controlled only by AGC action caused by the target itself even in the presence of interference.

Claim 5

Dependent Claim 256 words

A system as in claim 1 wherein the memory and delayed AGC circuit comprises: a. an input terminal to which AGC from the normal radar system is fed, b. an output terminal which is connected to said IF amplifier, c. first, second, and third relay switch means, which are normally closed, closed, and open respectively when in their normal unenergized mode during target tracking, d. said input terminal connected to one side of said first and third relay switches, e. an RC integration circuit, f. said second relay switch connected between the other side of said first relay switch and the input to said RC circuit, g. a cathode follower circuit whose output is connected to said output terminal, h. the output of said RC circuit and the other side of said third relay switch connected to the input to said cathode follower circuit, i. AGC voltage from the normal radar system being connected to said output terminal via said first and second relays, RC circuit, and cathode follower circuit during normal target tracking said AGC voltage being delayed and also continuously stored by said RC circuit, j. said third relay means being operable to be energized to close by any of manual and automatic tracking control means, k. said sEcond relay means being operable to be energized to open by control signals from the counter-countermeasure circuitry, l. a coincidence circuit means connected to said first relay means for energizing said first relay switch to open when any of chaff and gate stealer interference is encountered.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-03-10	1978-09-09	1979-03-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-03-10	1982-09-09	1983-03-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-03-10	1986-09-09	1987-03-11	$7700.00	Window Closed / Lapsed

Automatic gain integrator control

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