Automatic step eliminator circuit to prevent radar jamming

Claim 1

An automatic step eliminator circuit to prevent tracking radar jamming comprised of an intermediate frequency amplifier having a gain control input and a signal input, said intermediate amplifier receiving a normal target signal and a jamming signal by way of said signal input, a box car circuit receiving the output signal from said intermediate frequency amplifier, an automatic gain amplifier, a filter and delay network, said automatic gain amplifier receiving the output from said box car circuit and providing an output signal for reception by said filter and delay network, said gain control input of said intermediate amplifier receiving an actuating signal from said filter and delay network, a gate generator receiving an actuating signal from said automatic gain control amplifier to provide a square wave instruction signal in response thereto, first and second sample and hold amplifiers simultaneously receiving said square wave instruction signal, said first and second sample and hold amplifiers also simultaneously receiving input signals from said filter and delay network, said sample and hold amplifiers being controlled by said square wave instruction signal to store said normal target signal in said first sample and hold amplifier and said jamming signal in said second sample and hold amplifier, means to sum the output signals from said first and second sample and hold amplifiers to provide a continuous resultant signal to eliminate the alternate lack of an error signal, and error detector means receiving said continuous resultant signal.