Digital speed control system utilizing a countdown register

Claim 2

A digital speed control system for maintaining a desired speed of a controlled apparatus comprising, in combination, a memory register for storing a binary number; means for supplying a first pulse train having a number of pulses representing the desired speed of the controlled apparatus to the memory register, wherein the first pulse train steps the memory register to generate therein a binary number representing the desired speed of the controlled apparatus; a countdown register; means for cyclically transferring the binary number stored within the memory register to the countdown register, supplying a second pulse train having a number of pulses representing the actual speed of the controlled apparatus to the countdown register, and clearing the countdown register, wherein the second pulse train steps the countdown register to generate therein a binary number representing a controlled apparatus speed error; and means responsive to the binary number representing a controlled apparatus speed error for maintaining the desired speed.

Claim 3

A digital speed control system for maintaining a desired speed of a controlled apparatus comprising, in combination, a memory register for storing a binary number; means for generating a series of pulses having a frequency related to the speed of the controlled apparatus; means for supplying the series of pulses to the memory register for a specified duration of time when the speed of the controlled apparatus is at the desired speed, wherein the series of pulses steps the memory register to generate therein a binary number representing the desired speed; a countdown register; means for cyclically transferring the binary number stored within the memory register to the countdown register, supplying the series of pulses to the countdown register for the specified duration of time, and clearing the countdown register, wherein the series of pulses steps the countdown register to generate therein a binary number representing the difference between the desired speed and the actual speed of the controlled apparatus; and means responsive to the binary number representing the difference between the desired speed and the actual speed of the controlled apparatus for maintaining the desired speed.

Claim 4

A digital speed control system for maintaining a desired speed of a controlled apparatus comprising, in combination, a memory register for storing a binary number; means for generating a series of pulses having a frequency related to the speed of the controlled apparatus; means for supplying the series of pulses to the memory register for a specified duration of time when the speed of the controlled apparatus is at the desired speed, wherein the series of pulses steps the memory register to generate therein a binary number representing the desired speed; a countdown register; means for cyclically transferring the binary number stored within the memory register to the countdown register, supplying the series of pulses to the countdown register for the specified duration of time, and clearing the countdown register, wherein the series of pulses steps the countdown register to generate therein a binary number representing the difference between the desired speed and the actual speed of the controlled apparatus; and means responsive to the binary number representing the difference between the desired speed and the actual speed of the controlled apparatus for maintaining the desired speed.

Claim 5

The apparatus in claim 2 whereby the controlled apparatus is comprised of a vehicle having an internal combustion engine and means for supplying fuel thereto and the means responsive to the binary number representing the difference between the desired speed and the actual speed of the controlled apparatus includes the means for supplying fuel to the internal combustion engine.

Claim 6

A digital speed control system for maintaining a desired speed of a controlled apparatus comprising, in combination, a memory register for storing a binary number; means for generating a series of pulses having a frequency related to the speed of the controlled apparatus; means for supplying the series of pulses to the memory register for a specified duration of time when the speed of the contrOlled apparatus is at the desired speed, wherein the series of pulses steps the memory register to generate therein a binary number representing the desired speed; a countdown register; means for cyclically transferring the binary number stored within the memory register to the countdown register, supplying the series of pulses to the countdown register for the specified duration of time, and clearing the countdown register, wherein the series of pulses steps the countdown register to generate therein a binary number representing the difference between the desired speed and the actual speed of the controlled apparatus; and means responsive to the binary number generated within the countdown register for providing maximum acceleration or maximum deceleration when the error between the actual speed and the desired speed exceeds a predetermined magnitude and for providing varying degrees of acceleration or deceleration when the error between the actual speed and the desired speed is less than the predetermined magnitude, whereby the means responsive to the binary number generated within the countdown register is operative to maintain the desired speed.

Claim 7

A digital speed control system for maintaining a desired speed of a controlled apparatus comprising, in combination, a memory register for storing a binary number; means for generating a series of pulses having a frequency related to the speed of the controlled apparatus; means for supplying the series of pulses to the memory register for a specified duration of time when the speed of the contrOlled apparatus is at the desired speed, wherein the series of pulses steps the memory register to generate therein a binary number representing the desired speed; a countdown register; means for cyclically transferring the binary number stored within the memory register to the countdown register, supplying the series of pulses to the countdown register for the specified duration of time, and clearing the countdown register, wherein the series of pulses steps the countdown register to generate therein a binary number representing the difference between the desired speed and the actual speed of the controlled apparatus; and means responsive to the binary number generated within the countdown register for providing maximum acceleration or maximum deceleration when the error between the actual speed and the desired speed exceeds a predetermined magnitude and for providing varying degrees of acceleration or deceleration when the error between the actual speed and the desired speed is less than the predetermined magnitude, whereby the means responsive to the binary number generated within the countdown register is operative to maintain the desired speed.

Claim 10

A digital speed control system for maintaining a desired speed of a controlled apparatus comprising, in combination, a memory register for storing a binary number; means for generating a series of pulses having a frequency related to the speed of the controlled apparatus; means for supplying the series of pulses to the memory register for a specified duration of time when the speed of the controlled apparatus is at the desired speed, wherein the series of pulses steps the memory register to generate therein a binary number representing the desired speed; a countdown register having a plurality of stages; means for cyclically transferring the binary number stored within the memory register to respective stages in the countdown register, supplying the series of pulses to the countdown register for a specified duration of time, and clearing the countdown register, wherein the series of pulses steps the countdown register to generate therein a binary number representing the difference between the desired speed and the actual speed of the controlled apparatus; inverter means coupled to a selected number of the stages in the countdown register; means coupled to the selected number of stages in the countdown register and the inverter means for providing varying degrees of acceleration or deceleration of the controlled apparatus when the difference between the desired speed and the actual speed of the controlled apparatus is less than a predetermined magnitude; and means responsive to the binary number generated within the countdown register for providing maximum acceleration or maximum deceleration when the error between the actual speed and the desired speed of the controlled apparatus exceeds the predetermined magnitude.

Claim 11

A digital speed control system for maintaining a desired speed of a controlled apparatus comprising, in combination, a memory register for storing a binary number; means for generating a series of pulses having a frequency related to the speed of the controlled apparatus; means for supplying the series of pulses to the memory register for a specified duration of time when the speed of the controlled apparatus is at the desired speed, wherein the series of pulses steps the memory register to generate therein a binary number representing the desired speed; a countdown register having a plurality of stages; means for cyclically transferring the binary number stored within the memory register to respective stages in the countdown register, supplying the series of pulses to the countdown register for a specified duration of time, and clearing the countdown register, wherein the series of pulses steps the countdown register to generate therein a binary number representing the difference between the desired speed and the actual speed of the controlled apparatus; inverter means coupled to a selected number of the stages in the countdown register; means coupled to the selected number of stages in the countdown register and the inverter means for providing varying degrees of acceleration or deceleration of the controlled apparatus when the difference between the desired speed and the actual speed of the controlled apparatus is less than a predetermined magnitude; and means responsive to the binary number generated within the countdown register for providing maximum acceleration or maximum deceleration when the error between the actual speed and the desired speed of the controlled apparatus exceeds the predetermined magnitude.

Claim 12

A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: means for generating a first digital signal responsive to the actual speed of the vehicle comprising a series of speed signal pulses having a pulse repetition frequency proportional to the speed of the vehicle; means for generating a second digital signal responsive to a constant preselected vehicle speed comprising a digital reference clock, a first digital counter and means for clocking said first digital counter in response to said first digital signal during a first given reference clock period, thereby storing in said first digital counter a first digital number responsive to the preselected speeds of the vehicle; means for digitally comparing the first digital signal responsive to the actual speed of the vehicle and the second digital signal responsive to the constant preselected vehicle speed to produce a digital error signal, wherein said means comprises a second digital counter, means for loading said second digital counter with said first digital number at the beginning of a second given reference clock period, means for clocking said second digital counter in response to said first digital signal during said second given reference clock period, and means responsive to said second digital counter for producing said digital error signal; and means for adjusting the speed of the vehicle in response to said digital error signal to maintain the preselected constant speed.

Claim 13

A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: means for generating a first digital signal responsive to the actual speed of the vehicle comprising a series of speed signal pulses having a pulse repetition frequency proportional to the speed of the vehicle; means for generating a second digital signal responsive to a constant preselected vehicle speed comprising a digital reference clock, a first digital counter and means for clocking said first digital counter in response to said first digital signal during a first given reference clock period, thereby storing in said first digital counter a first digital number responsive to the preselected speeds of the vehicle; means for digitally comparing the first digital signal responsive to the actual speed of the vehicle and the second digital signal responsive to the constant preselected vehicle speed to produce a digital error signal, wherein said means comprises a second digital counter, means for loading said second digital counter with said first digital number at the beginning of a second given reference clock period, means for clocking said second digital counter in response to said first digital signal during said second given reference clock period, and means responsive to said second digital counter for producing said digital error signal; and means for adjusting the speed of the vehicle in response to said digital error signal to maintain the preselected constant speed.

Claim 14

A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: a. means for generating a series of digital speed pulses having a repetition rate proportional to the actual speed of the vehicle; b. a digital reference clock; c. a digital memory counter; d. means for clocking said digital counter in response to said speed pulses during a given reference clock period for storing in said digital counter a first digital number representative of a pre-selected vehicle speed; e. a counting register; f. means for cyclically transferring the first digital number from said digital counter to said register and for clocking said register in response to said speed pulses representative of the actual vehicle speed under the control of said digital clock for the given reference clock period to produce a digital error signal; and g. a throttle actuator for adjusting the speed of the vehicle in response to said digital error signal to maintain the selected speed.

Claim 15

A digital speed control for maintaining a motor vehicle at a preselected constant speed comprising: a. means for generating a series of digital speed pulses having a repetition rate proportional to the actual speed of the vehicle; b. a digital reference clock; c. a digital memory counter; d. means for clocking said digital counter in response to said speed pulses during a given reference clock period for storing in said digital counter a first digital number representative of a pre-selected vehicle speed; e. a counting register; f. means for cyclically transferring the first digital number from said digital counter to said register and for clocking said register in response to said speed pulses representative of the actual vehicle speed under the control of said digital clock for the given reference clock period to produce a digital error signal; and g. a throttle actuator for adjusting the speed of the vehicle in response to said digital error signal to maintain the selected speed.