US3868647A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Elimination of transient errors in a data processing system by clock control
Assignee: Digital Equipment Corp
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Filing: 1973-05-16
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Granted: 1975-02-25
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Expires: 1993-05-16
Abstract
Abstract A repeat is performed in a computer system after detection of an error in the operation, the circumstances then being changed as much as possible. The clock frequency is then decreased by the selective blocking of a part of the clock pulses, so that second clock pulse cycles are produced which are composed of the same but wider spaced clock pulses. All functions remain possible duringthe second clock pulse cycles, be it at a lower speed. The circumstances can be further modified yet by first completely stopping the computer system for a given period of time, or by erasing the information sorted in a foreground store.
Inventors
- 👤 Frederik Zandveld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:31
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141; G06F1/00; G06F1/04; G06F1/08; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
158 words
In a data processing system having a control unit, a clock for generating clock pulses and a data processor which is controlled by said clock pulses and wherein the data processor also comprises an error detector for detecting processing errors, said system also including means to reset the control unit to a prior operational position by control of an error signal generated by the error detector and means internal to the control unit to restart the data processor by an appropriate restart signal, the improvement comprising means responsive to the error signal for generating an intermediate signal in addition to the restart signal, and means responsive to said intermediate signal and responsive to the clock for generating clock pulses having a repetition time which exceeds that of the clock pulses provided prior to the appearance of the error signal, whereby the processor may be operated at the faster clock rate so that transient processing errors may be avoided.
Claim 2
Dependent Claim
158 words
In a data processing system having a control unit, a clock for generating clock pulses and a data processor which is controlled by said clock pulses and wherein the data processor also comprises an error detector for detecting processing errors, said system also including means to reset the control unit to a prior operational position by control of an error signal generated by the error detector and means internal to the control unit to restart the data processor by an appropriate restart signal, the improvement comprising means responsive to the error signal for generating an intermediate signal in addition to the restart signal, and means responsive to said intermediate signal and responsive to the clock for generating clock pulses having a repetition time which exceeds that of the clock pulses provided prior to the appearance of the error signal, whereby the processor may be operated at the faster clock rate so that transient processing errors may be avoided.
Claim 3
Dependent Claim
46 words
A data processing system as claimed in claim 1, wherein a delay element is provided responsive to the error signal for generating the restarting signal after a predetermined delay, and means being provided for blocking the clock pulses between the error signal and the restarting signal.
Claim 4
Dependent Claim
41 words
A data processing system as claimed in claim 1, including a foreground store and a main store which cooperate with said control unit and processor, wherein the information of the foreground store can be erased in response to said error signal.
Claim 5
Dependent Claim
178 words
In a data processing system having a control unit, a clock for generating clock pulses and a data processor which is controlled by said clock pulses and wherein the data processor also comprises an error detector for detecting processing errors, said system also including means to reset the control unit to a prior operational position by control of an error signal generated by the error detector and means internal to the control unit to restart the data processor bY an appropriate restart signal, the improvement comprising means responsive to the error signal for generating an intermediate signal in addition to the restart signal, and means responsive to said intermediate signal and responsive to the clock for generating clock pulses and wherein the clock includes means for generating cycles of clock pulses, and means responsive to said intermediate signal for alternately blocking and allowing passage of clock pulses during an integer number of clock pulse cycles so as to form a second cycle of clock pulses which are composed of corresponding clock pulses and which have a longer duration.
Claim 6
Dependent Claim
178 words
In a data processing system having a control unit, a clock for generating clock pulses and a data processor which is controlled by said clock pulses and wherein the data processor also comprises an error detector for detecting processing errors, said system also including means to reset the control unit to a prior operational position by control of an error signal generated by the error detector and means internal to the control unit to restart the data processor bY an appropriate restart signal, the improvement comprising means responsive to the error signal for generating an intermediate signal in addition to the restart signal, and means responsive to said intermediate signal and responsive to the clock for generating clock pulses and wherein the clock includes means for generating cycles of clock pulses, and means responsive to said intermediate signal for alternately blocking and allowing passage of clock pulses during an integer number of clock pulse cycles so as to form a second cycle of clock pulses which are composed of corresponding clock pulses and which have a longer duration.
Claim 7
Dependent Claim
52 words
A data processing system as claimed in claim 4, in which a cycle consists of n clock pulses, and wherein during a (kn+1)-multiple of said cycles alternately one clock pulse can be allowed to pass by the intermediate signal and kn clock-pulses can be blocked (where k 1,2 . . . ).
Claim 8
Dependent Claim
27 words
A data processing system as claimed in claim 4, including means for developing third cycles of clock pulses responsive to blocking signals formed from the intermediate signal.
References Cited (Backward Citations)
US3453601A
Cited
US3623017A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-24 | 1978-08-26 | 1979-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-24 | 1982-08-26 | 1983-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-24 | 1986-08-26 | 1987-02-25 | $7700.00 | Window Closed / Lapsed |