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US3866170A
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Binary transmission system using error-correcting code
Assignee: Italtel SpA
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Filing: 1973-09-24
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Granted: 1975-02-11
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Expires: 1993-09-24
Abstract
Abstract A 6-bit binary word is fed into a coder including a 5-stage shift register for the five lowest-ranking bits and a flip-flop for the highest-ranking one. The register has feedback connections from its third and fifth stages to its input, including an Exclusive-OR gate, causing its fifth stage to read out a recurrent 31-bit maximum sequence in response to a train of stepping pulses. Depending on the value of the sixth bit stored in the flip-flop, another Exclusive-OR gate delivers either this sequence or its complement to a transmitter. On the receiving side, the arriving sequence is compared with the output of a similar feedback-connected shift register which is periodically loaded with a reference combination such as 11111 and which, upon every 33rd stepping pulse, starts one of 31 different permutations of a 31-bit maximum sequence which is thereupon compared bit by bit with the incoming sequence. In the event of a match with an original sequence or its complement, there are either 31 or 0 coincidences between bits; in all other instances the number of coincidences is 15 in the case of an original sequence and 16 in the case of its complement. In order to allow for transmission errors of up to 7 bits per sequence, the comparator works into a numerical discriminator generating an output signal if the number of coincidences per cycle. is at least 24 or not more than 7. The output signal, occurring just after the 31st stepping pulse, causes the readout of the contents of the associated shift register into a register upon the 32nd stepping pulse which re-establishes the word present therein at the beginning of the matching permutation. The register then contains the first five bits of the reconstituted word whose sixth bit is determined by the high or low count of the comparator.
Inventors
- 👤 Federico Verzocchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:19
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H04L1/0041; H04L1/0045
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
448 words
A system for the transmission of binary words, each word consisting of n + 1 bits, comprising: a first shift register with n stages for receiving n bits of a word to be transmitted; first feedback means connected to said first shift register for sequentially developing an n-bit combination stored therein into an invariable cyclic succession of 2n-1 n-bit combinations starting with the combination originally stored; first stepping means connected to said first feedback means for driving said first shift register through a full cycle of 2n-1 combinations with resulting generation of a maximum sequence of 2n-1 bits in any stage thereof; a second shift register provided with second feedback means, said first and second feedback means each comprising an Exclusive-OR gate with input connections to the nth stage and to a lower-ranking stage of the associated shift register; second stepping means substantially duplicating said first shift register, first feedback means and first stepping means, respectively, for generating maximum comparison sequences of 2n-1 bits each; timing means operable at the beginning of a frame of at least 2n-1 cycles of said second stepping means for introducing into said second shift register an n-bit reference combination recurring every 2n-1 steps, each cycle of said second stepping means consisting of a number of steps greater than 2n-1 whereby each cycle of a frame begins with a different starting combination in said second shift register; storage means connected to said receIving means for preserving an incoming maximum sequence over 2n-1 cycles of said second stepping means; comparator means connected to said storage means and to a stage of said second shift register for successively comparing the bits of said incoming maximum sequence with the bits of all 2n1 comparison sequences emitted by the last-mentioned stage in the course of a frame, said comparator means including a counter for registering the number of bit coincidences between said incoming sequence and any one comparison sequence; numerical discriminator means connected to said counter for generating an output signal upon the number of bit coincidences in any cycle of said second stepping means deviating by more than a predetermined amount from a mismatch-indicating count of ((2n 1-1)/2) + OR - 1/2 ; output means connected to said discriminating means and controlled by said timing means for extracting from said second shift register the starting combination of the cycle in which said output signal is generated; and an ancillary stage for the (n+1)th bit of a word and a further Exclusive-OR gate with input connections to said one stage of said first shift register and to said ancillary stage for converting the generated maximum sequence into its complement in the presence of a finite (n+1)th bit.
Claim 2
Independent Claim
448 words
A system for the transmission of binary words, each word consisting of n + 1 bits, comprising: a first shift register with n stages for receiving n bits of a word to be transmitted; first feedback means connected to said first shift register for sequentially developing an n-bit combination stored therein into an invariable cyclic succession of 2n-1 n-bit combinations starting with the combination originally stored; first stepping means connected to said first feedback means for driving said first shift register through a full cycle of 2n-1 combinations with resulting generation of a maximum sequence of 2n-1 bits in any stage thereof; a second shift register provided with second feedback means, said first and second feedback means each comprising an Exclusive-OR gate with input connections to the nth stage and to a lower-ranking stage of the associated shift register; second stepping means substantially duplicating said first shift register, first feedback means and first stepping means, respectively, for generating maximum comparison sequences of 2n-1 bits each; timing means operable at the beginning of a frame of at least 2n-1 cycles of said second stepping means for introducing into said second shift register an n-bit reference combination recurring every 2n-1 steps, each cycle of said second stepping means consisting of a number of steps greater than 2n-1 whereby each cycle of a frame begins with a different starting combination in said second shift register; storage means connected to said receIving means for preserving an incoming maximum sequence over 2n-1 cycles of said second stepping means; comparator means connected to said storage means and to a stage of said second shift register for successively comparing the bits of said incoming maximum sequence with the bits of all 2n1 comparison sequences emitted by the last-mentioned stage in the course of a frame, said comparator means including a counter for registering the number of bit coincidences between said incoming sequence and any one comparison sequence; numerical discriminator means connected to said counter for generating an output signal upon the number of bit coincidences in any cycle of said second stepping means deviating by more than a predetermined amount from a mismatch-indicating count of ((2n 1-1)/2) + OR - 1/2 ; output means connected to said discriminating means and controlled by said timing means for extracting from said second shift register the starting combination of the cycle in which said output signal is generated; and an ancillary stage for the (n+1)th bit of a word and a further Exclusive-OR gate with input connections to said one stage of said first shift register and to said ancillary stage for converting the generated maximum sequence into its complement in the presence of a finite (n+1)th bit.
Claim 3
Dependent Claim
24 words
A system as defined in claim 1 wherein n 5, said lower-ranking stage lying between the first and fourth stages of the shift register.
Claim 4
Dependent Claim
95 words
A system as defined in claim 1 wherein said discriminating means comprises logical circuitry for generating an output signal of a first kind upon the number of bit coincidences exceeding 2n-2-e and an output signal of a second kind upon the number of bit coincidences being less than e + 1, e being a measure of maximum permissible error and being at most equal to 2n 2-1, further comprising supplemental output means connected to said discriminating means for indicating the value of the (n + 1)th bit according to the kind of output signal generated.
Claim 5
Dependent Claim
39 words
A system as defined in claim 1, further comprising zero-detection means connected to said discriminating means and controlled by said timing means for indicating an all-zero bit combination upon the absence of said output signal over an entire frame.
Claim 6
Dependent Claim
44 words
A system as defined in claim 1 wherein said storage means comprises a pair of buffer registers of 2n-1 stages each controlled by writing and reading signals from said timing means for alternately storing an incoming sequence and reading out a sequence previously stored.
Claim 7
Dependent Claim
40 words
A system as defined in claim 5 wherein each of said buffer registers is a shift register with a feedback connection closed in a reading phase for recirculating the stored sequence, said feedback connection being opened in a writing phase.
Claim 8
Dependent Claim
30 words
A system as defined in claim 1 wherein said transmission means and said comparator means are connected to the nth stage of said first and said second shift register, respectively.
Claim 9
Dependent Claim
74 words
A system as defined in claim 1 wherein said timing means delivers 2n-1 stepping pulses per cycle to said storage means and a final pulse at the end of each cycle to said output means for actuating same, said second stepping means being connected to receive both said stepping pulses and said final pulse from said timing means whereby the number of steps taken by said second shift register during each cycle equals 2n.
References Cited (Backward Citations)
US3373404A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |