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US3866029A
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Two level random number generator having a controllable expected value
Assignee: Prayfel Inc
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Filing: 1973-09-18
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Granted: 1975-02-11
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Expires: 1993-09-18
Abstract
Abstract A random number generator for generating a sequence of binary random numbers (Si) whose expected value is controlled by an input digital number x. The random number generator includes a random bit generator which generates at one output a sequence of mutually independent random variables (RBi) such that the probability P(RBi 0) P(RBi 1) 1/2 . Means are further provided to sequentially analyze the sequence of random variables (RBi) and generate a random variable Li which has a probability function given by P(Li k) 2 k where k 1, 2, 3 . . . each time a pattern of the form (1000 . . . 01) containing (k - 1) zero is detected. Means are further provided to set the output random variable Si of the random number generator equal to the bit Xk of x whenever the random variable Li is equal to k, and this for k 1, 2, 3 . . . .
Inventors
- 👤 Paul Chevalier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:01
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/58
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
146 words
A random number generator for generating a sequence of binary random numbers (Si) whose expected value is controlled by an input digital number x, comprising: a random bit generator which generates at one output a sequence of mutually independent random variables (RBi) such that the probability P(RBi 0) P(RBi 1) 1/2 , means to sequentially analyse the sequence of random variables (RBi) and generate a random variable Li which has a probability function given by: P(Li k) 2 k where k 1, 2, 3 . . . each time a pattern of the form ( 1,000 . . . 01) containing (k1) zero is detected, and means to set the output random variable Si of said random number generator equal to the bit Xk of x whenever the random variable Li is equal to k, and this for k 1, 2, 3, . . . .
Claim 2
Dependent Claim
146 words
A random number generator for generating a sequence of binary random numbers (Si) whose expected value is controlled by an input digital number x, comprising: a random bit generator which generates at one output a sequence of mutually independent random variables (RBi) such that the probability P(RBi 0) P(RBi 1) 1/2 , means to sequentially analyse the sequence of random variables (RBi) and generate a random variable Li which has a probability function given by: P(Li k) 2 k where k 1, 2, 3 . . . each time a pattern of the form ( 1,000 . . . 01) containing (k1) zero is detected, and means to set the output random variable Si of said random number generator equal to the bit Xk of x whenever the random variable Li is equal to k, and this for k 1, 2, 3, . . . .
Claim 3
Dependent Claim
42 words
A random number generator as claimed in claim 1 in which there is further provided a second output to indicate if the random variable Si at the output of the random number generator is independent of the previous random variable Si 1.
Claim 4
Dependent Claim
56 words
A random number generator as claimed in claim 1 wherein said random bit generator has a flag bit signal (NBi) at another output which indicates if the bit (RBi) at its said one output is independent of the previous bit RBi 1; said flag signal being utilized to inhibit the sequential processing when it is clear.
Claim 5
Dependent Claim
69 words
A random number generator as claimed in claim 1 wherein said means to sequentially analyse the sequence (RBi) is a latch memory circuit fed by a counter, the counter being clear when said bit (RBi) 1 and incremented by one when said bit (RBi) 0, said latch memory circuit being loaded with the contents of said counter when said bit (RBi) 1 and disabled when said bit (RBi) 0.
Claim 6
Dependent Claim
54 words
A random number generator as claimed in claim 1 wherein the said means to set the output variable Si equal to the bit Xk of x is a multiplexer circuit controlled by the output Li of a latch memory circuit, said multiplexer having a data input fed by the bits of the word x.
Claim 7
Dependent Claim
59 words
A random number generator as claimed in claim 1 wherein said means to sequentially analyse the sequence (RBi) is a counter which is cleared when (RBi) 1 and incremented by one when (RBi) 0, a latch memory circuit is connected to the output of a multiplexer circuit to generate the random variable Si when RBi becomes equal to 1.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |