Dual computer system with signal exchange system

Claim 1

A dual computer system for highly reliable use in industrial process instrumentation for complex processes having a number of variable process conditions such as temperature, flow rate, and the like, and arranged to receive signals representing the values of various process conditions, the store data comprising programs and base data for performing computations respecting process conditions, and to produce corresponding output signals for use in controlling the process, said dual computer system comprising: a pair of synchronized central processors, one of which acts as a principal central processor and the other of which acts as an auxiliary central processor, each central processor comprising an arithmetic and control unit, having registers for data storage, a main memory unit for data storage, a memory bus which connects the arithemtic and control unit with the main memory unit, means for exchanging memory data signals on the memory bus between the main memory unit and the registers of the arithmetic and control unit, and input/output terminals for receiving input data signals into and transferring output data signals from the arithmetic and control unit; input/output devices for exchanging process input/output data signals with the dual computer system; a data bus line connecting to the input/output devices; data bus exchange means for controlling the connections between the input/output terminals of the principal and auxiliary central processors and the data bus line; a memory bus exchange means for controlling the connections between the memory bus of the principal central processor and the memory bus of the auxiliary central processor and thereby allowing the two central processors to exchange memory data signals; and a dual control unit supplied with the output data signals from the arithmetic and control units of the two central processors and arranged to control the data bus exchange means and memory bus exchange means, said dual control unit comprising a clock circuit for synchronizing the pair of central processors, means responsive to the output data signals from the two arithmetic and control units of the two central processors for detecting a lack of coincidence therebetween corresponding to the failure of one of the central processors, means responsive to detection of lack of coincidence between said output data signals for causing the data bus exchange means to disconnect the data bus line from both central processors, means including diagnostic programs stored in both central processors and operating upon detection of lack of coincidence between said output data signals for determining the failed central processor, means responsive to said failure determination means for causing the data bus exchange means to connect the data bus line with the input/output terminals of the normal central processor for resumption of computations respecting process conditions by the normal central processor while the failed central processor undergoes repair, means for controlling the memory bus exchange means to transfer memory data signals from the normal central processor to a repaired central processor to equalize the memory of the repaired central processor with the instantaneous memory content of the operating normal central processor, and means for starting the repaired central processor with equalized memory to cause it to opErate in synchronism with the normal central processor and to cause the data bus exchange means to supply input data signals to both arithmetic and control units, whereby if a fault occurs in one of the central processors, the faulty central processor is located, repaired and restored to dual operation, and either of the two central processors is responsible for input/output operations, except for short intervals during error diagnosis, whereby the two central processors provide a very reliable and effective dual computer system for process control.