Patent US3864669A successfully refreshed from Google Patents.
US3864669A
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US
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Correction arrangement for electronic typewriters
Assignee: BUHMANN ELEKTRO APP WALTER
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Filing: 1972-09-11
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Granted: 1975-02-04
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Expires: 1992-09-11
Abstract
Abstract The alpha-numeric symbols and function signals required for the final automatic typing in an electronic typewriter are stored as code words in a plurality of circulating shift registers, one for each binary place of the code word. When a symbol (code word) is to be inserted into or deleted from the stored sequence of code words, the number of stages of each shift register is temporarily, respectively, increased or decreased by one stage. For an insertion, the proper instant at which to enter the code word to be inserted is determined by a comparator output. The comparator input compares the count on a register counter counting the synchronizing pulses shifting the information through the shift registers to the count on an address counter. The count on the address counter signifies the position on the paper being typed upon at which the insertion is to be made.
Inventors
- 👤 Klaus Schlickeiser
- 👤 Hartmut Linke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:16
CPC Classifications
B; B41; B41J; B41J3/00; B41J3/44; B41J3/50; B41J5/00; B41J5/30; B41J5/44
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
415 words
In a system for furnishing a visual output corresponding to selected ones of a plurality of alphanumeric inputs each represented by a code word having a predetermined number of places, and having function control means for furnishing a selected one of a plurality of function signals including a ''''write'''' signal and a ''''delete'''' signal upon external activation, a correction arrangement for deleting from said visual output a determined one of said alpha-numeric inputs, comprising, in combination, memory means for storing said code words, said memory means comprising a plurality of synchronously operable circulating storage means, one for each of said places, each having a determined plurality of storage locations arranged in a predetermined order, said plurality of storage locations including a first storage location, a last storage location, a next to the last storage location immediately preceding said last storage location in said predetermined order, and a third last storage location immediately preceding said next to the last storage location in said predetermined order; synchronizing means connected to said memory means, for furnishing synchronizing signals to said plurality of synchronously operable circulating storage means in such a manner that said storage means transfers information from each of said storage locations to the next subsequent one of said storage locations in said predetermined order in response to each of said synchronizing signals; first counting means connected to said synchronizing means for counting said synchronizing signals and furnishing a first counting signal signifying the number of so-counted synchronizing signals; externally operable address signal furnishing means for furnishing address signals each signifying one of said storage locations in said predetermined order; coMparator means connected to said address signal and furnishing a comparator output signal when said first counting signal corresponds to said address signal; memory control means connected to said comparator means, said function control means and said memory means for selectively connecting the outputs of said last or next to the last storage locations to said first storage locations under control of said function signals and said comparator output signal in such a manner that said last storage location is disconnected from said first storage location when the code word representing said determined one of said alpha-numeric inputs is in said last storage location, whereby said code word is deleted from the sequence of code words stored in said memory means; and output means connected to said memory means for furnishing said visual output in correspondence to said sequence of code words stored in said memory means.
Claim 2
Dependent Claim
415 words
In a system for furnishing a visual output corresponding to selected ones of a plurality of alphanumeric inputs each represented by a code word having a predetermined number of places, and having function control means for furnishing a selected one of a plurality of function signals including a ''''write'''' signal and a ''''delete'''' signal upon external activation, a correction arrangement for deleting from said visual output a determined one of said alpha-numeric inputs, comprising, in combination, memory means for storing said code words, said memory means comprising a plurality of synchronously operable circulating storage means, one for each of said places, each having a determined plurality of storage locations arranged in a predetermined order, said plurality of storage locations including a first storage location, a last storage location, a next to the last storage location immediately preceding said last storage location in said predetermined order, and a third last storage location immediately preceding said next to the last storage location in said predetermined order; synchronizing means connected to said memory means, for furnishing synchronizing signals to said plurality of synchronously operable circulating storage means in such a manner that said storage means transfers information from each of said storage locations to the next subsequent one of said storage locations in said predetermined order in response to each of said synchronizing signals; first counting means connected to said synchronizing means for counting said synchronizing signals and furnishing a first counting signal signifying the number of so-counted synchronizing signals; externally operable address signal furnishing means for furnishing address signals each signifying one of said storage locations in said predetermined order; coMparator means connected to said address signal and furnishing a comparator output signal when said first counting signal corresponds to said address signal; memory control means connected to said comparator means, said function control means and said memory means for selectively connecting the outputs of said last or next to the last storage locations to said first storage locations under control of said function signals and said comparator output signal in such a manner that said last storage location is disconnected from said first storage location when the code word representing said determined one of said alpha-numeric inputs is in said last storage location, whereby said code word is deleted from the sequence of code words stored in said memory means; and output means connected to said memory means for furnishing said visual output in correspondence to said sequence of code words stored in said memory means.
Claim 3
Dependent Claim
55 words
A system as set forth in claim 1, wherein said output means comprise display means having a plurality of display locations corresponding in number to the number of said determined plurality of storage locations in each of said storage means, whereby each of said display locations corresponds to a corresponding one of said storage locations.
Claim 4
Dependent Claim
43 words
A system as set forth in claim 2, wherein said output means comprise control means operative in response to said comparator output signal to furnish a visual output corresponding to the code word stored in the storage location signified by said address signal.
Claim 5
Dependent Claim
202 words
A system as set forth in claim 3, wherein said correction arrangement is further an arrangement for adding to said visual output a selected one of said alpha-numeric inputs; wherein said storage means each comprise a shift register having a plurality of stages each constituting one of said storage locations, said stages including a last stage, a next to the last stage and a third last stage respectively corresponding to said last, next to the last and third last storage locations; wherein said function control signals further include a ''''isert'''' signal; and wherein said memory control means comprise first circuit means for connecting the output of said next to the last stage to the input of said first stage in the presence of said ''''write'''' signal and under control of said comparator output signal, second circuit means for connecting the output of said last stage to the input of said first stage in the presence of said ''''insert'''' signal and under control of said comparator output signal, and third circuit means for connecting the output of said third last stage to the input of said first stage in the presence of said ''''delete'''' signal and under control of said comparator output signal.
Claim 6
Dependent Claim
30 words
A system as set forth in claim 4, wherein each of said first stages has an input; further comprising input/output control means connected to said inputs of said shift registers.
Claim 7
Dependent Claim
31 words
A system as set forth in claim 5, wherein said input/output control means comprise a plurality of input/output control units, one connected to the input of each of said shift registers.
Claim 8
Dependent Claim
289 words
A system as set forth in claim 6, wherein said memory control means comprise first OR-gate means having an output connected to said output control means, and a first, second and third input, and blocking circuit means having a blocking circuit output and a first and second blocking circuit input, said blocking circuit means having a set state in response to a signal at said first blocking circuit input and a reset state in response to a signal at said second blocking circuit input, said blocking circuit means furnishing a blocking signal when in said set state; and wherein said first, second and third circuit means respectively comprise first, second and third AND-gate means each having an output connected to a corresponding input of said first OR-gate means, a function control input connected to said function control means in such a manner that said function conTrol input of said first, second and third AND-gate means is enabled, respectively, in response to said ''''write,'''' ''''insert'''' and ''''delete'''' signals respectively, a blocking input connected to said blocking circuit output, and a register input connected, respectively, to said next to the last, last, and third last register stages; first inverter means interconnected between said blocking circuit output and said blocking input of said first AND-gate means; first connecting means for connecting said first blocking circuit input to said comparator means; and second connecting means for connecting said second blocking circuit input to said first counting means for resetting said blocking circuit means upon receipt of a ''''0'''' count on said first counting means, whereby said memory control means operate to increase or decrease the number of stages in said shift register until completion of the operating cycle having a deletion or insertion.
Claim 9
Dependent Claim
28 words
A system as set forth in claim 4, further comprising indicator means connected to said registers, for furnishing an indicator signal signifying the number of empty storage locations.
Claim 10
Dependent Claim
61 words
A system as set forth in claim 8, wherein a predetermined code word stored in said storage means signifies an empty storage location; further comprising additional counting means interconnected between said registers and said indicator means, for counting said predetermined code words and furnishing a corresponding counting signal; and wherein said indicator means furnish a visual indication of said counting signal.
Claim 11
Dependent Claim
37 words
A system as set forth in claim 9, further comprising additional register means interconnected between said additional counting means and said indicator means, for furnishing the final counting signal in each operating cycle to said indicator means.
Claim 12
Dependent Claim
47 words
A system as set forth in claim 4, further comprising additional storage means; and means connected to said additional storage means and said synchronously operable circulating storage means for transferring said sequence of code words from said synchronously operable circulating storage means to said additional storage means.
Claim 13
Dependent Claim
114 words
A system as set forth in claim 1, wherein an operating cycle constitutes circulating of one of said code words through all of said storage locations; wherein a ''''0'''' count signal on said first counting means signifies the beginning of one of said operating cycles; and wherein said memory control means comprise first memory control means for connecting said next to the last storage location to said first storage location in the presence of said ''''write'''' signal, and second memory control means for connecting said last storage location to said first storage location from receipt of said ''''0'''' count signal until receipt of said comparator output signal in the presence of said ''''delete'''' signal.
Claim 14
Dependent Claim
86 words
A system as set forth in claim 12, wherein said connection arrangement further constitutes an arrangement for adding to said visual output a determined one of said alpha-numeric inputs; wherein said function control means further furnish a ''''insert'''' signal; and wherein said second memory control means comprise means connected to said function control means, for connecting said last memory location to said first memory location from receipt of said comparator output signal to receipt of said ''''0'''' count signal in the presence of said ''''insert'''' signal.
Claim 15
Dependent Claim
235 words
A system as set forth in claim 13, wherein said memory control means comprise OR-gate means having an output connected to said first storage location, and a first, second and third input, and first and second blocking circuit means, each having a set and reset input and an output carrying a ''''1'''' signal upon receipt of a signal at said set input, means for applying said ''''0'''' count signal to said reset input of said first blocking means and said set input of said second blocKing means; means for applying said comparator output signal to said set input of said first blocking circuit means and said reset input of said second blocking circuit means; wherein said first memory control means comprise first AND-gate means having a first input connected to said next to the last storage location, a second input connected to said function control means for receiving said ''''write'''' signal, and a third input connected to said outputs of said first and second blocking means; and wherein said second memory control means comprises second AND-gate means having an output connected to said OR-gate, a first input connected to said last storage location, a second input connected to said function control means for receiving said ''''delete'''' and ''''insert'''' signals, and a third input; further comprising inverter means connecting said third input of said second AND-gate means to said set outputs of said blocking circuit means.
Claim 16
Dependent Claim
218 words
A system as set forth in claim 13, wherein said memory control means comprise OR gate means having an output connected to the input of said first stage, and a first, second and third input, and first and second blocking circuit means, each having a set and reset input and output; means applying said ''''0'''' count signal to said reset input of said first blocking means and said set input of said second blocking means; means applying said comparator output signal to said set input of said first blocking circuit means and said reset input of said second blocking circuit means; wherein said first memory control means comprise first AND gate means having a first input connected to said next to the last storage location, a second input connected to receive said ''''write'''' signal, and a third input connected to said set outputs of said first and second blocking means; and wherein said second memory control means comprises second AND gate means having an output connected to said OR gate, a first input connected to said last storage location, a second input connected to receive said ''''delete'''' and '''' insert'''' signals, and a third input; further comprising inverter means connecting said third input of said second AND gate means to said set outputs of said blocking circuit means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-03 | 1978-08-05 | 1979-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-03 | 1982-08-05 | 1983-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-03 | 1986-08-05 | 1987-02-04 | $7700.00 | Window Closed / Lapsed |