US3864582A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mosfet dynamic circuit
Assignee: Timex Group USA Inc
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Filing: 1973-01-22
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Granted: 1975-02-04
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Expires: 1993-01-22
Abstract
Abstract An integrated complementary MOS transistor circuit is used to divide an input frequency by a factor or two, and similar circuits may be used as counters or shift registers. The circuit is dynamic, low in power consumption, and is based upon one or more inverters which operate in the pulsed power mode.
Inventors
- 👤 Eugene R Keeler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:21
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
179 words
A divide-by-two dynamic counter circuit consisting of at least three inverters, each of which is a complementary pair of MOSFET transistors, each of said transistors having a control gate electrode and a drain electrode, and a source electrode; the circuit including a first pair of such transistors, each of which has its source electrodes connected to respective sources of reversing relative polarity so that each source receives reversals of polarity which are out-of-phase in respect to each other; a second pair of such transistors, each of such second pair of transistors having its gate electrode connected to between common drain electrodes of said first pair and whose source electrodes are connected to said respective sources of reversing polarity and whose drain electrodes are connected together; and a third pair of such transistors whose gate electrodes are both connected to said common drain electrodes of said second pair; the output being taken at the common drain electrodes of said third pair, and the gate electrodes of said first pair being connected to the common drain electrodes of said third pair.
Claim 2
Dependent Claim
179 words
A divide-by-two dynamic counter circuit consisting of at least three inverters, each of which is a complementary pair of MOSFET transistors, each of said transistors having a control gate electrode and a drain electrode, and a source electrode; the circuit including a first pair of such transistors, each of which has its source electrodes connected to respective sources of reversing relative polarity so that each source receives reversals of polarity which are out-of-phase in respect to each other; a second pair of such transistors, each of such second pair of transistors having its gate electrode connected to between common drain electrodes of said first pair and whose source electrodes are connected to said respective sources of reversing polarity and whose drain electrodes are connected together; and a third pair of such transistors whose gate electrodes are both connected to said common drain electrodes of said second pair; the output being taken at the common drain electrodes of said third pair, and the gate electrodes of said first pair being connected to the common drain electrodes of said third pair.
Claim 3
Dependent Claim
182 words
A count-down divide-by-two dynamic integrated circuit consisting of a least four inverters each of which is a complementary pair of MOS transistors, each of said transistors having a control gate electrode, a source electrode and a drain electrode, the circuit including a first pair of such transistors, each of which has its gate electrodes connected to respective sources of out-of-phase reversing relative polarity, a second pair of complementary transistors, each of such second pairs of such transistors having its gate electrodes connected to a common connection of the drain electrodes of said first pair and its source electrodes connected to said respective polarity reversal sources; a third pair of such transistors whose gate electrodes are both connected to the drain electrodes of said second pair; and a fourth pair of such transistors, each of the gate elctrodes of such fourth pair being connected to the common drain electrodes of said third pair; the output being taken at said drain electrodes of said fourth pair, and the drain electrodes of said fourth pair being connected to the source electrodes of said first pair.
Claim 4
Dependent Claim
182 words
A count-down divide-by-two dynamic integrated circuit consisting of a least four inverters each of which is a complementary pair of MOS transistors, each of said transistors having a control gate electrode, a source electrode and a drain electrode, the circuit including a first pair of such transistors, each of which has its gate electrodes connected to respective sources of out-of-phase reversing relative polarity, a second pair of complementary transistors, each of such second pairs of such transistors having its gate electrodes connected to a common connection of the drain electrodes of said first pair and its source electrodes connected to said respective polarity reversal sources; a third pair of such transistors whose gate electrodes are both connected to the drain electrodes of said second pair; and a fourth pair of such transistors, each of the gate elctrodes of such fourth pair being connected to the common drain electrodes of said third pair; the output being taken at said drain electrodes of said fourth pair, and the drain electrodes of said fourth pair being connected to the source electrodes of said first pair.
References Cited (Backward Citations)
US3524077A
Cited
US3716723A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-03 | 1978-08-05 | 1979-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-03 | 1982-08-05 | 1983-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-03 | 1986-08-05 | 1987-02-04 | $7700.00 | Window Closed / Lapsed |