US3864529A — Receiver for decoding duobinary signals

Claim 1

Independent Claim 205 words

In a receiver for converting duobinary signals to binary data, a self-correcting clock circuit comprising: a. a source of duobinary signals; b. a source of strobe signals; c. comparator means connected to said signal sources so as to compare the level of said duobinary signal at the node of its ''''eye'''' pattern to a plurality of predetermined reference levels; d. clock means for producing clock pulses, said strobe signals having the same frequency as said clock pulses; e. means for varying the frequency of said clock means; f. binary logic means connected to said comparator means and said clock means for producing a binary timing correction output in accordance with the relation of the center sample of a sample sequence representing a + OR - 1, 0, - OR + 1 transition of the duobinary analog signal to one of said reference levels; and g. integrator means connected to said logic means for integrating said binary correction output over a substantial number of cycles; h. the output of said integrator means being connected to said clock-frequency-varying means to vary said frequency in such a manner as to shift the phase of said strobe signals to keep them centered upon the node of the duobinary ''''eye.''''

Claim 2

Dependent Claim 205 words

In a receiver for converting duobinary signals to binary data, a self-correcting clock circuit comprising: a. a source of duobinary signals; b. a source of strobe signals; c. comparator means connected to said signal sources so as to compare the level of said duobinary signal at the node of its ''''eye'''' pattern to a plurality of predetermined reference levels; d. clock means for producing clock pulses, said strobe signals having the same frequency as said clock pulses; e. means for varying the frequency of said clock means; f. binary logic means connected to said comparator means and said clock means for producing a binary timing correction output in accordance with the relation of the center sample of a sample sequence representing a + OR - 1, 0, - OR + 1 transition of the duobinary analog signal to one of said reference levels; and g. integrator means connected to said logic means for integrating said binary correction output over a substantial number of cycles; h. the output of said integrator means being connected to said clock-frequency-varying means to vary said frequency in such a manner as to shift the phase of said strobe signals to keep them centered upon the node of the duobinary ''''eye.''''

Claim 3

Dependent Claim 45 words

The device of claim 1, in which said reference levels are 0 and + or - 1/2 of the nominal logic ''''1'''' level of the duobinary signal at said node, and in which the reference level to which said center sample is related is 0.

Claim 4

Dependent Claim 74 words

The device of claim 1, in which said logic means include first and second shift registers connected to said comparator means, said first shift register being connected to receive an input pulse whenever said duobinary signal, at the moment of sampling, is > + 1/2 or < - 1/2 ; and said second shift register being connected to receive an input pulse whenever said duobinary signal, at the moment of sampling, is > 0.

Claim 5

Dependent Claim 84 words

The device of claim 3, in which said logic means are connected to produce a timing correction output pulse one sample interval in length only whenever the contents of said first shift register are 101, and the contents of said second shift register are such as to indicate a zero-crossing of said duobinary signal just prior to the center sampling instant; and a timing correction pulse one-half sample interval in length only whenever the contents of said first shift register are other than 101.

Claim 6

Dependent Claim 47 words

The device of claim 4, in which said second shift register is a three-bit register, and in which a timing correction pulse one-half sample interval in length is also produced whenever the first and third bit of the contents of said second shift register are the same.

Claim 7

Dependent Claim 38 words

The device of claim 4, in which the zero-crossing of said duobinary signal prior to the center sampling instant is indicated by the fact that the first and second bit of said second shift register are the same.

Claim 8

Dependent Claim 22 words

The device of claim 4, in which said logic means, except for said shift registers, consist entirely of NOR and OR/NOR gates.

Claim 9

Dependent Claim 24 words

The device of claim 4, in which said logic means, except for said shift registers, consist entirely of EXCLUSIVE-OR, EXCLUSIVE-NOR, NOR, and OR/NOR gates.

Claim 10

Independent Claim 233 words

The method of maintaining the sample timing in a duobinary to binary converter at the node of the ''''eye'''' pattern of the duobinary signal, comprising the steps of: a. generating a clock signal by electronic apparatus; b. generating a delayed clock signal from said clock signal by electronic apparatus; c. electronically employing said clock signal and said delayed clock signal to sample said duobinary signal in the vicinity of successive nodes of the ''''eye'''' pattern; d. employing electronic apparatus to compare the sampLes to predetermined signal level ranges to determine, for each sample, whether it is highly positive (+1), highly negative (-1), or near zero (0), to compare successive samples in groups of three to identify three-sample sequences (+1, 0, -1 or -1, 0, +1) which necessarily contain a zero transition of said doubinary signal, and to compare the center sample of each thus identified sequence to a zero signal level to determine the sign of the center sample; e. electronically generating, for each thus identified sequence, a digital timing correction signal in accordance with the sign of the center sample in relation to the signs of the other two samples; f. employing electronic apparatus to integrate said digital timing correction signal over a substantial number of sequences; and g. applying said integrated timing correction signal to said electronic apparatus for generating said clock signal to vary the frequency of said clock signal.

Claim 11

Independent Claim 233 words

The method of maintaining the sample timing in a duobinary to binary converter at the node of the ''''eye'''' pattern of the duobinary signal, comprising the steps of: a. generating a clock signal by electronic apparatus; b. generating a delayed clock signal from said clock signal by electronic apparatus; c. electronically employing said clock signal and said delayed clock signal to sample said duobinary signal in the vicinity of successive nodes of the ''''eye'''' pattern; d. employing electronic apparatus to compare the sampLes to predetermined signal level ranges to determine, for each sample, whether it is highly positive (+1), highly negative (-1), or near zero (0), to compare successive samples in groups of three to identify three-sample sequences (+1, 0, -1 or -1, 0, +1) which necessarily contain a zero transition of said doubinary signal, and to compare the center sample of each thus identified sequence to a zero signal level to determine the sign of the center sample; e. electronically generating, for each thus identified sequence, a digital timing correction signal in accordance with the sign of the center sample in relation to the signs of the other two samples; f. employing electronic apparatus to integrate said digital timing correction signal over a substantial number of sequences; and g. applying said integrated timing correction signal to said electronic apparatus for generating said clock signal to vary the frequency of said clock signal.

Claim 12

Independent Claim 193 words

The method of maintaining the sample timing in a duobinary to binary converter at the node of the ''''eye'''' pattern of the duobinary signal, comprising the steps of: a. generating a clock signal by electronic apparatus; b. generating a delayed clock signal from said clock signal by electronic apparatus; c. electronically employing said clock signal and said delayed clock signal to sample said duobinary signal in the vicinity of successive nodes of the ''''eye'''' pattern; d. employing electronic apparatus to detect a + or - 1, 0, -or + 1 sequence in three successive samples; e. employing electronic apparatus to detect the sign of said duobinary signal at the center sample; f. electronically generating a digital timing correction signal in accordance with the detected sign of the center sample relative to the signs of the other two samples when a + or -1, 0, - or + 1 sequence is detected; g. employing electronic apparatus to integrate said digital timing correction signal over a substantial number of sequences; and h. applying said integrated timing correction signal to said electronic apparatus for generating said clock signal to vary the frequency of said clock signal.

Claim 13

Independent Claim 193 words

The method of maintaining the sample timing in a duobinary to binary converter at the node of the ''''eye'''' pattern of the duobinary signal, comprising the steps of: a. generating a clock signal by electronic apparatus; b. generating a delayed clock signal from said clock signal by electronic apparatus; c. electronically employing said clock signal and said delayed clock signal to sample said duobinary signal in the vicinity of successive nodes of the ''''eye'''' pattern; d. employing electronic apparatus to detect a + or - 1, 0, -or + 1 sequence in three successive samples; e. employing electronic apparatus to detect the sign of said duobinary signal at the center sample; f. electronically generating a digital timing correction signal in accordance with the detected sign of the center sample relative to the signs of the other two samples when a + or -1, 0, - or + 1 sequence is detected; g. employing electronic apparatus to integrate said digital timing correction signal over a substantial number of sequences; and h. applying said integrated timing correction signal to said electronic apparatus for generating said clock signal to vary the frequency of said clock signal.

Claim 14

Dependent Claim 36 words

The method of claim 10, comprising the farther step of electronically generating a self-cancelling digital timing correction signal whenever the detected sequence of samples is other than + or - 1, 0, - or + 1.

Claim 15

Dependent Claim 91 words

The method of claim 11, in which said digital timing correction signal when generated consists of a full-bit pulse when the second and third samples of said three-sample sequence are of opposite signs, and said sequence is + or - 1, 0, - or + 1; a half-bit pulse when said sequence is other than + or - 1, 0, - or + 1; and no pulse when said second and third samples are of the same sign, and said sequence is + or - 1, 0, - or + 1.

Claim 16

Dependent Claim 32 words

The method of claim 11, comprising the further step of also electronically generating said self-cancelling digital timing signal whenever the first and last samples of a sequence are of the same sign.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1978-02-03	1978-08-05	1979-02-04	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1982-02-03	1982-08-05	1983-02-04	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1986-02-03	1986-08-05	1987-02-04	$7700.00	Window Closed / Lapsed

Receiver for decoding duobinary signals

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