US3863331A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Matching of semiconductor device characteristics
Assignee: RCA Corp
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Filing: 1972-09-11
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Granted: 1975-02-04
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Expires: 1992-09-11
Abstract
Abstract Characteristics of photolithographically-defined planar semiconductor device pairs made from the same master are different, but many of the differences are regular in kind. To achieve a device pair in which the magnitude of the difference in the characteristics of the elements of the pair is reduced, two pairs are made from the same master. The first element of one pair is connected to the second element of the other pair so that the two operate as one composite element. The second element of the one pair is connected to the first element of the other, similarly for operation as another composite element the characteristics of which closely match those of the one composite element.
Inventors
- 👤 Jr Otto Heinrich Schade
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:59
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; H10P; H10P95/00; Y; Y10; Y10S; Y10S257/00; Y10S257/919; Y10S438/00; Y10S438/942
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
143 words
A method of making an electrical circuit which includes a pair of circuit elements having closely matched characteristics comprising: forming, by photolithographic processes using at least one photomask, two pairs of subelements, each pair including a first subelement and a second subelement, said first subelements being made by using a pair of separate patterns on said photomask, each of said first pair of separate patterns on said photomask being made from a first pattern on a master, said second subelements being made by using a second pair of sEparate patterns on said photomask, each of said second pair of said separate patterns being made from a second pattern on said master, and connecting the first subelement of one pair with the second subelement of the other pair and the second subelement of said one pair with the first subelement of the other pair.
Claim 2
Independent Claim
143 words
A method of making an electrical circuit which includes a pair of circuit elements having closely matched characteristics comprising: forming, by photolithographic processes using at least one photomask, two pairs of subelements, each pair including a first subelement and a second subelement, said first subelements being made by using a pair of separate patterns on said photomask, each of said first pair of separate patterns on said photomask being made from a first pattern on a master, said second subelements being made by using a second pair of sEparate patterns on said photomask, each of said second pair of said separate patterns being made from a second pattern on said master, and connecting the first subelement of one pair with the second subelement of the other pair and the second subelement of said one pair with the first subelement of the other pair.
Claim 3
Dependent Claim
26 words
A method as defined in claim 1 wherein both said pairs of said subelements are formed by processes performed on one common body of semiconductive material.
Claim 4
Dependent Claim
131 words
A method as defined in claim 2 wherein said photomask is made by a process including the steps of, designing a master for said device including a first zone of predetermined area in which said first and second patterns are disposed and a second zone of at least the same predetermined area, said second zone being entirely opaque, and making a photomask from said master by making an exposure of a photosensitive means with said master, said second zone preventing exposure of a portion of said photosensitive means, protecting the exposed portions of said photosensitive means from re-exposure, repositioning said master to orient said first zone with respect to the unexposed portion of said photosensitive means, and making an exposure of said unexposed portion with said first zone of said master.
Claim 5
Independent Claim
157 words
A method of making an electrical circuit which includes a pair of circuit elements having closely matched characteristics comprising: forming a photolithographic master having a pair of like pattern arrangements thereon, forming a photomask from said master by a repetitive exposure thereof such that said photomask has at least two pairs of said pair of like pattern arrangements, exposing a photoresist coating on a semiconductor wafer with said photomask, said exposing step together with other steps making at least two pairs of subelements, each of said pair of subelements corresponding to the said pair of like pattern arrangements in said master and include a first subelement and a second subelement, and connecting the first subelement of one pair with the second subelement of the other pair to form one of said circuit elements and the second subelement of said one pair with the first subelement of the other pair to form the other of said circuit elements.
Claim 6
Independent Claim
157 words
A method of making an electrical circuit which includes a pair of circuit elements having closely matched characteristics comprising: forming a photolithographic master having a pair of like pattern arrangements thereon, forming a photomask from said master by a repetitive exposure thereof such that said photomask has at least two pairs of said pair of like pattern arrangements, exposing a photoresist coating on a semiconductor wafer with said photomask, said exposing step together with other steps making at least two pairs of subelements, each of said pair of subelements corresponding to the said pair of like pattern arrangements in said master and include a first subelement and a second subelement, and connecting the first subelement of one pair with the second subelement of the other pair to form one of said circuit elements and the second subelement of said one pair with the first subelement of the other pair to form the other of said circuit elements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-03 | 1978-08-05 | 1979-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-03 | 1982-08-05 | 1983-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-03 | 1986-08-05 | 1987-02-04 | $7700.00 | Window Closed / Lapsed |