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US3863233A
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Magnetic memory array
Assignee: Lockheed Martin Tactical Systems Inc
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Filing: 1973-03-23
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Granted: 1975-01-28
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Expires: 1993-03-23
Abstract
Abstract An associative processor is provided which is a digital computer system capable of operating upon many independent sets of data at once or simultaneously. Each data set is processed sequentially, bit by bit giving an overall effect that is analogous to a large bank of serial computers all executing the same program, but on different data. Each memory word corresponds to one such serial processor. Since the available number of memory words greatly exceeds the number of data bits typically processed in parallel by a conventional sequential computer, the associative processor has a considerable speed advantage. Each word in memory has a common response store and arithmetic unit to accomplish logical operations in a parallel by word serial by bit interrogation. In essence, the processor combines an associative memory with control of the associative memory provided through essentially parallel input-output busses, and with the associative memory array incorporating arithmetic and logic circuits. These logic circuits permit parallel by word, serial by bit readout, thus incorporating an input/output capability that exceeds all prior computer techniques.
Inventors
- 👤 Everett E Eddey
- 👤 James N Favor
- 👤 Willard C Meilander
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:24
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/02; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8038
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
275 words
Apparatus for storing, accessing, and processing a plurality of data simultaneously within a memory array having a first set of wires wherein each wire is common to all bits of one word and a second set of wires wherein each wire is common to one bit of all words and having first and second sets of current drivers wherein each current driver of the first set is connected to a different wire of the first set of wires and each current driver of the second set is connected to a different wire of the second set of wires, the wire drivers being operative to access data storage bits of the array, comprising: a plurality of identical circuit means connected to the array, one such circuit means connected to each of the wires of the first set of wires for retrieving data therefrom and performing upon such data all sixteen of the logic and arithmetic functions possible between two bits of data, said circuit means including: sensing means, one connected to each of the wires to the first set of wires, for sensing data of the bits of the associated word; a gating means connected to the sensing means and having a first flip-flop receiving the outputs thereof, the gating means having a timed binary pulse applied thereto such that the binary state of the first flip-flop is indicative of the output of the sensing means and the pulse timing; and a second flip-flop and an output gate connected to and receiving the outputs of the first and second flip-flops, the second flip-flop controlling the passage of data from the first flipflop through the output gate.
Claim 2
Dependent Claim
275 words
Apparatus for storing, accessing, and processing a plurality of data simultaneously within a memory array having a first set of wires wherein each wire is common to all bits of one word and a second set of wires wherein each wire is common to one bit of all words and having first and second sets of current drivers wherein each current driver of the first set is connected to a different wire of the first set of wires and each current driver of the second set is connected to a different wire of the second set of wires, the wire drivers being operative to access data storage bits of the array, comprising: a plurality of identical circuit means connected to the array, one such circuit means connected to each of the wires of the first set of wires for retrieving data therefrom and performing upon such data all sixteen of the logic and arithmetic functions possible between two bits of data, said circuit means including: sensing means, one connected to each of the wires to the first set of wires, for sensing data of the bits of the associated word; a gating means connected to the sensing means and having a first flip-flop receiving the outputs thereof, the gating means having a timed binary pulse applied thereto such that the binary state of the first flip-flop is indicative of the output of the sensing means and the pulse timing; and a second flip-flop and an output gate connected to and receiving the outputs of the first and second flip-flops, the second flip-flop controlling the passage of data from the first flipflop through the output gate.
Claim 3
Dependent Claim
50 words
The apparatus as recited in claim 1 wherein the first set of wires comprises a plurality of plated wires and a second set of wires comprise a plurality of bit straps, the bit straps crossing over the plated wires and defining data storage bits at the resultant points of crossover.
Claim 4
Dependent Claim
45 words
The apparatus as recited in claim 1 wherein each of the plated wires has adjacent thereto a return wire and wherein pairs of adjacent wires share a common termination point at one of their ends and are common to said sensing means at the other.
Claim 5
Dependent Claim
59 words
The apparatus as recited in claim 1 wherein the second flip-flop has associated therewith two control pulses, a first control pulse operative to set the state of the second flip-flop independent of the first flip-flop and a second control pulse operative to set the state of the second flip-flop as a function of the state of the first flip-flop.
Claim 6
Dependent Claim
58 words
The apparatus as recited in claim 1 wherein the first and second flip-flops are further connected to first and second writing gates, the second flip-flop being operative to simultaneously enable both writing gates, and the first flip-flop being operative to enable one of the writing gates in a mutually exclusive manner with regard to the other writing gate.
Claim 7
Dependent Claim
35 words
The apparatus as recited in claim 1 wherein the outputs of the first flip-flop and gatedly connected to the inputs of the first and second flip-flops of another of the plurality of identical circuit means.
Claim 8
Dependent Claim
28 words
The apparatus as recited in claim 1 which includes a third flip-flop connected to the first flip-flop, the third flip-flop providing a tag bit for the circuit means.
Claim 9
Dependent Claim
135 words
Apparatus for achieving the parallel processing of a plurality of data, comprising: a magnetic memory array having bit-comprised data storage words; and a plurality of identical circuit means, one connected to each of the data storage words and capable of performing the sixteen logic and arithmetic functions possible between two bits of data, and circuit means including: sensing means connected to the data storage word for sensing data therefrom; a first flip-flop gatedly connected to the sensing means for receiving data therefrom and producing an output indicative thereof; a second flip-flop connected to the first flip-flop and an output gate for selectively passing the output of the first flip-flop through the output gAte; and writing means connected to the first and second circuit means and the data storage word for writing data into the array.
Claim 10
Dependent Claim
135 words
Apparatus for achieving the parallel processing of a plurality of data, comprising: a magnetic memory array having bit-comprised data storage words; and a plurality of identical circuit means, one connected to each of the data storage words and capable of performing the sixteen logic and arithmetic functions possible between two bits of data, and circuit means including: sensing means connected to the data storage word for sensing data therefrom; a first flip-flop gatedly connected to the sensing means for receiving data therefrom and producing an output indicative thereof; a second flip-flop connected to the first flip-flop and an output gate for selectively passing the output of the first flip-flop through the output gAte; and writing means connected to the first and second circuit means and the data storage word for writing data into the array.
Claim 11
Dependent Claim
39 words
The apparatus as recited in claim 8 which further includes a gating circuit connected to the first flip-flop of another of the identical circuit means, the gating circuit providing the capability of shifting data between the various circuit means.
Claim 12
Dependent Claim
49 words
The apparatus as recited in claim 8 wherein the writing means comprises first and second gates connected to a bi-polar driver, the second flip-flop enabling both gates simultaneously and the first flip flop enabling one of the gates in a mutually exclusive manner with respect to the other gate.
References Cited (Backward Citations)
US3360788A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-27 | 1978-07-29 | 1979-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-27 | 1982-07-29 | 1983-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-27 | 1986-07-29 | 1987-01-28 | $7700.00 | Window Closed / Lapsed |