US3863227A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and arrangement for testing a core memory
Assignee: AG Communication Systems Corp
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Filing: 1973-09-17
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Granted: 1975-01-28
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Expires: 1993-09-17
Abstract
Abstract A method and arrangement for selecting and testing each one of the individual electronic control elements used to access all of the different core elements in a core memory, while the memory is ''''on-line.'''' A 16K word memory is disclosed, and the individual electronic control elements are tested by using an address pattern which identifies each one of 512 words, these words being accessed in four different modes. The address pattern also is such that it can be easily identified.
Inventors
- 👤 Rafael A Sanabria
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:51
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
274 words
A method of testing a memory system including a core memory having a plurality of cores as storage elements and electronic control elements including a plurality of digit drivers, digit switches, word drivers and word switches for accessing said plurality of cores to write words into said core memory locations defined by an address and to read said words out of said core memory, comprising the steps of: (a) selecting a predetermined number of address locations within said core memory during online operation for testing, said predetermined address locations being interlaced with other address locations currently being used for the normal storage of data; (b) writing each one of a group of words one-at-a-time into said selected address locations, each of said written words including data bits corresponding to the address bits of a selected location into which said words are written, by combining the selection of predetermined ones of said digit drivers, digit switches, word drivers and word switches in a fashion such that each one of said digit drivers is tested with each one of said digit switches and each one of said word drivers is tested with each one of said word switches; (c) subsequently reading each of said written words from said core memory; (d) comparing the address of each of said selected locations with said words as they are read from said core memory to determine whether the words and the addresses are the same; (e) whereby all of said electronic control elements can be tested aNd the operation thereof verified by writing a group of words which is less in number than the capacity of the core memory.
Claim 2
Independent Claim
274 words
A method of testing a memory system including a core memory having a plurality of cores as storage elements and electronic control elements including a plurality of digit drivers, digit switches, word drivers and word switches for accessing said plurality of cores to write words into said core memory locations defined by an address and to read said words out of said core memory, comprising the steps of: (a) selecting a predetermined number of address locations within said core memory during online operation for testing, said predetermined address locations being interlaced with other address locations currently being used for the normal storage of data; (b) writing each one of a group of words one-at-a-time into said selected address locations, each of said written words including data bits corresponding to the address bits of a selected location into which said words are written, by combining the selection of predetermined ones of said digit drivers, digit switches, word drivers and word switches in a fashion such that each one of said digit drivers is tested with each one of said digit switches and each one of said word drivers is tested with each one of said word switches; (c) subsequently reading each of said written words from said core memory; (d) comparing the address of each of said selected locations with said words as they are read from said core memory to determine whether the words and the addresses are the same; (e) whereby all of said electronic control elements can be tested aNd the operation thereof verified by writing a group of words which is less in number than the capacity of the core memory.
Claim 3
Dependent Claim
127 words
The method of claim 1, further including the steps of (a) identifying each of said selected address locations by an address bit which establishes the phase of the current flow through said cores, (b) including a data bit which is the same as said address bit establishing the phase of current flow through said cores as part of each of said words written into said selected address locations, and (c) establishing the same address bit for each of said selected address locations so that the same current phase is used to access each of said selected address locations, whereby only one-half the number of selected address locations which would have to be accessed if the current phase is reversed need be accessed to test said memory system.
Claim 4
Dependent Claim
76 words
The method of claim 1, further including the step of combining the selection of a digit driver and a digit switch to be tested with a word switch to be tested in a fashion such that the data bits of said written word identifying the digit driver and the digit switch correspond to and are the same as the data bits of said written word identifying the word switch, whereby a recognizable address pattern is created.
Claim 5
Dependent Claim
150 words
The method of claim 1, further including the steps of (a) including within each of said written words data bits which are the same as the address bits which identify one of said selected locations, a parity bit and a plurality of additional address bits which duplicate other ones of the address bits identifying the selected location such that the repetition of said address bits will always force parity to one of two established parity values; (c) each of said words being written one-at-a-time into said selected locations to force the parity to a first one of said established parity values and then the complement of each of said words being subsequently written one-at-a-time into said selected locations to force the parity to the second one of said established parity values; whereby parity can be thereby tested by forcing the parity value to each of the two established parity values.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-01-27 | 1978-07-29 | 1979-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-01-27 | 1982-07-29 | 1983-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-01-27 | 1986-07-29 | 1987-01-28 | $7700.00 | Window Closed / Lapsed |