Sample peak and hold with dual current source

Claim 2

A circuit for charging a capacitor to a predetermined percentage of the peak amplitude of an input signal comprising: voltage sensitive means coupled to said capacitor and receiving said input signal for comparing the charge on said capacitor with said input signal and for identifying a first level of charge and a second level of charge on said capacitor as percentages of peak amplitude of said input signals; means for supplying current at a high-charging rate and current at a low-charging rate to said capacitor; first means activable by said voltage sensitive means for controlling said current-supplying means to provide current at said high-charging rate to said capacitor up to said first level of charge when said first activable means is activated; second means activable by said voltage sensitive means for controlling said current-supplying means to provide current at said low-charging rate to said capacitor up to said second level of charge when said second activable means is activated and said first activable means is inactivated; said current-supplying means being disabled when said first and second activable means are both inactivated.

Claim 3

The charging circuit of claim 1, wherein said voltage sensitive means includes: first and second voltage dividers for respectively determining said first and second levels of charge; and first and second differential comparators for respectively identifying said first and second levels of charge, each of said comparators having a non-inverting input and an inverting input, said non-inverting input of said second comparator receiving said input signal and being coupled to the non-inverting input of said first comparator through said second voltage divider, and the inverting input of said first comparator being coupled to said capacitor and through said first voltage divider to the inverting input of said second comparator.

Claim 4

The charging circuit of claim 1, wherein said current-supplying means comprises variable impedance means including: a main current-carrying circuit for interconnecting a voltage source to said capacitor; and a control circuit interconnecting said main current-carrying circuit and said first and second activable means for controlling said current-supplying means.

Claim 5

The charging circuit of claim 3, wherein the main current-carrying circuit of said variable impedance means includes: a solid-state current control element having a first main current-carrying electrode resistively coupled to said capacitor, and a second main current-carrying electrode for interconnection to a voltage source.

Claim 6

The charging circuit of claim 4, wherein the control circuit of said variable impedance means further includes: a control electrode for said solid-state element; and a unidirectional connection between said second main current-carrying electrode and said control electrode of said solid-state element.

Claim 7

The charging circuit of claim 5, wherein said unidirectional connection includes a first parallel circuit having a resistive element and a unidirectional impedance element in parallel.

Claim 8

The charging circuit of claim 6, wherein said solid-state current-control element is a PNP transistor and wherein said variable impedance means further includes a third voltage divider for interconnecting the emitter of said transistor to positive voltage source, and wherein said control circuit further includes a second parallel circuit including diode means and a second resistive element in parallel for obtaining a predetermined voltage drop, said second parallel circuit being connected between said first parallel circuit and said third voltage divider.

Claim 9

The charging circuit of claim 6, wherein said first activable means is a first switching means driven by the output of said first differential comparator for placing said variable impedance means in a high-current mode when said first switching means is conductive; and said second activable means is a second switching means driven by the output of said second differential comparator for placing said variable impedance means in a low current mode, when said second switching means is conductive and said first switching means is nonconductive; said main current-carrying circuit being disabled when both said first and second switching means are nonconductive, the charging circuit thereby being in a standby condition.

Claim 10

The charging circuit of claim 8, wherein: said first switching means, when conductive, interconnects a reference potential to said unidirectional connection of said variable impedance means between one end of said first parallel circuit and said control electrode; and said second switching means, when conductive, interconnects a reference potential to said unidirectional connection at the other end of said first parallel circuit.

Claim 11

A sample, peak and hold circuit comprising: a storage capacitor; voltage sensitive means coupled to said capacitor and receiving an input signal for comparing the charge on said capacitor with said input signal and for identifying a first level of charge and a second level of charge on said capacitor as percentages of peak amplitude of said input signals; means for supplying a high-charging current and a low-charging current to said capacitor; means connected between said voltage-sensitive means and said current-supplying means, and driven by said voltage sensitive means, for controlling said current-supplying means to initially provide said high-charging current to said capacitor up to said first level of charge, to next provide said low-charging current up to said second level of charge on said capacitor, and thereafter to disable said current-supplying means, placing said circuit in a standby condition; means connected to said capacitor for outputting a voltage representative of the charge upon said capacitor, while substantially maintaining said capacitor charge; means for discharging said capacitor; means for simultaneously actuating said discharging means and disabling said current-supplying means through said controlling means; and means independent of said actuating and disabling means for disabling said current-supplying means through said controlling means to place said sample peak and hold circuit in a holding condition.

Claim 12

A sample, peak and hold circuit comprising: a storage capacitor; voltage sensitive means coupled to said capacitor and receiving an input signal for comparing the charge on said capacitor with said input signal and for identifying a first level of charge and a second level of charge on said capacitor as percentages of peak amplitude of said input signals; means for supplying a high-charging current and a low-charging current to said capacitor; means connected between said voltage-sensitive means and said current-supplying means, and driven by said voltage sensitive means, for controlling said current-supplying means to initially provide said high-charging current to said capacitor up to said first level of charge, to next provide said low-charging current up to said second level of charge on said capacitor, and thereafter to disable said current-supplying means, placing said circuit in a standby condition; means connected to said capacitor for outputting a voltage representative of the charge upon said capacitor, while substantially maintaining said capacitor charge; means for discharging said capacitor; means for simultaneously actuating said discharging means and disabling said current-supplying means through said controlling means; and means independent of said actuating and disabling means for disabling said current-supplying means through said controlling means to place said sample peak and hold circuit in a holding condition.

Claim 13

The sample peak, and hold circuit of claim 10, wherein said voltage sensitive means includes: first and second voltage dividers for respectively determining said first and second levels of charge; and first and second differential comparators for respectively identifying said first and second levels of charge, each of said comparators having a non-inverting input and an inverting input, said non-inverting input of said second comparator receiving said input signal and being coupled to the non-inverting input of said first comparator through said second voltage divider, and the inverting input of said first comparator being coupled to an output of said outputting means and through said first voltage divider to the inverting input of said second comparator.

Claim 14

The sample, peak, and hold circuit of claim 10, wherein said current-supplying means comprises variable impedance means including: a main current-carrying circuit for interconnecting a voltage source to said capacitor; and a control circuit interconnecting said main current-carrying circuit and said means for controlling said current-supplying means.

Claim 15

The sample, peak, and hold circuit of claim 12, wherein the main current-carrying circuit of said variable impedance means includes: a solid-state current control element having a first main current-carrying electrode resistively coupled to said capacitor, and a second main current-carrying electrode for interconnection to a voltage source.

Claim 16

The sample, peak, and hold circuit of claim 13, wherein the control circuit of said variable impedance means, further includes: a control electrode for said solid-state element; and a unidirectional connection between said second main current-carrying electrode and said control electrode of said solid-state element.

Claim 17

The sample, peak, and hold circuit of claim 14, wherein said unidirectional connection includes a first parallel circuit having a resistive element and a unidirectional impedance element in parallel.

Claim 18

The sample, peak, and hold circuit of claim 15, wherein said solid-state current control element is a PNP transistor and wherein said variable impedance further includes a third voltage divider for interconnecting the emitter of said transistor to a positive voltage source, and wherein said control circuit further includes a second parallel circuit including diode means and a second resistive element in parallel, for obtaining a predetermined voltage drop, said second parallel circuit being connected between said first parallel circuit and said third voltage divider.

Claim 19

The sample, peak, and hold circuit of claim 15, wherein said means for controlling said current-supplying means includes: first switching means driven by the output of said first differential comparator for placing said variable impedance means in a high-current mode when said first switching means is conductive; and second switching means driven by the output of said second differential comparator for placing said variable impedance means in a low-current mode, when said second switching means is conductive and said first switching means is nonconductive; said main current-carry circuit being disabled when both said first and second switching means are nonconductive, the charging circuit thereby being in a standby condition.

Claim 20

The sample, peak, and hold circuit of claim 17, wherein said first switching means, when conductive, interconnects a reference potential to said unidirectional connection of said variable impedance means between one end of said first parallel circuit and said control electrode; and said second switching means, when conductive, interconnects a reference potential to said unidirectional connection at the other end of said first parallel circuit.

Claim 21

The sample, peak, and hold circuit of claim 10, wherein said outputting means includes a transistorized emitter-follower amplifier.

Claim 22

The sample, peak, and hold circuit of claim 17, wherein said discharging means includes: third switching means connected between said capacitor and said means for simultaneously actuating said discharging means and disabling said controlling means, said third switching means operating to resistively ground said capacitor.

Claim 23

The sample, peak, and hold circuit of claim 20, wherein said means for simultaneously actuating said discharging means and disabling said current-supplying means through said controlling means includes first logic means.

Claim 24

The sample, peak, and hold circuit of claim 21, wherein said first logic means includes: first, second, and third NAND gates, the inputs of said NAND gates being adapted to receive a first control signal; the outputs of said first and second NAND gates being connected to said first and second swItching means respectively; and the output of said third NAND gate being connected to said third switching means.

Claim 25

The sample, peak, and hold circuit of claim 22 wherein said independent means for placing said sample peak and hold circuit in a holding condition includes second logic means.

Claim 26

The sample, peak, and hold circuit of claim 23, wherein said second logic means includes: third and fourth NAND gates, the inputs of said third and fourth NAND gates being adapted to receive a second control signal; and the outputs of said third and fourth NAND gates being connected to said first and second switching means respectively.

Claim 27

The dual-current source of claim 24, wherein said unidirectional connection includes a parallel circuit having a resistive element and a unidirectional impedance means in parallel.

Claim 28

The dual current source of claim 25 wherein said first activable means is a first switch resistively connecting one end of said parallel circuit and the base of said transistor to ground for biasing said transistor into the high current mode when said first switch is conductive; and said second activable means is a second switch resistively connecting the other end of said parallel circuit to ground for biasing said transistor into the low-current mode, when said second switch is conductive and said first switch is non-conductive; said transistor being placed in a cut-off mode when said first and second switches are both non-conductive.

Claim 29

The dual-current source of claim 26, wherein said unidirectional impedance is a first diode having its cathode connected to the base of said transistor; and wherein said biasing circuit further includes diode means and a second resistive element in parallel connected in series between the anode of said first diode and said resistive voltage divider.

Claim 30

A dual-current source for selectively applying different magnitudes of current to a load comprising: a PNP transistor having its emitter coupled through a resistive voltage divider to a positive voltage source, and its collector connected to said load; a biasing circuit having a unidirectional connection between the base of said transistor and said voltage divider; first activable means for controlling said biasing circuit to place said transistor in a high-current mode when said first activable means is activated; and second activable means for controlling said biasing circuit to place said transistor in a low-current mode when said second activable means is activated and said first activable means is inactivated; said transistor being placed in a cutoff mode by said biasing circuit when said first and second activable means are both inactivated.

Claim 31

A dual-current source for selectively applying different magnitudes of current to a load comprising: a PNP transistor having its emitter coupled through a resistive voltage divider to a positive voltage source, and its collector connected to said load; a biasing circuit having a unidirectional connection between the base of said transistor and said voltage divider; first activable means for controlling said biasing circuit to place said transistor in a high-current mode when said first activable means is activated; and second activable means for controlling said biasing circuit to place said transistor in a low-current mode when said second activable means is activated and said first activable means is inactivated; said transistor being placed in a cutoff mode by said biasing circuit when said first and second activable means are both inactivated.

Claim 32

A dual-current source for selectively applying different magnitudes of current to a load, comprising: a positive voltage source; a PNP transistor having a collector, an emitter, and a base electrode, the collector electrode of said transistor being connected to said load; a first resistor; a second resistor joined in series with said first resistor to form a voltage divider, said voltage divider being connected between the positive voltage source and the emitter electrode of said transistor; a biasing circuit having a unidirectional connection between the base of said transistor and the junction of said first and second resistors in said voltage divider; first activable means for controlling said biasing circuit to place said transistor in a high current mode when said first activable means is activated; and second activable means for controlling said biasing circuit to place said transistor in a low current mode when said second activable means is activated and said first activable means is inactivated; said transistor being placed in a cut-off mode by said biasing circuit when said first and second activable means are both inactivated.

Claim 33

A dual-current source for selectively applying different magnitudes of current to a load, comprising: a positive voltage source; a PNP transistor having a collector, an emitter, and a base electrode, the collector electrode of said transistor being connected to said load; a first resistor; a second resistor joined in series with said first resistor to form a voltage divider, said voltage divider being connected between the positive voltage source and the emitter electrode of said transistor; a biasing circuit having a unidirectional connection between the base of said transistor and the junction of said first and second resistors in said voltage divider; first activable means for controlling said biasing circuit to place said transistor in a high current mode when said first activable means is activated; and second activable means for controlling said biasing circuit to place said transistor in a low current mode when said second activable means is activated and said first activable means is inactivated; said transistor being placed in a cut-off mode by said biasing circuit when said first and second activable means are both inactivated.